From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 11 Mar 2020 16:51:57 +0000 (+0000)
Subject: dewildcard stage.py
X-Git-Tag: div_pipeline~1713
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bdc41697d6804616b51bc6c327b570aa804e2ce0;p=soc.git

dewildcard stage.py
---

diff --git a/src/soc/minerva/stage.py b/src/soc/minerva/stage.py
index 33d941de..9144cc2b 100644
--- a/src/soc/minerva/stage.py
+++ b/src/soc/minerva/stage.py
@@ -1,8 +1,8 @@
 from functools import reduce
 from operator import or_
 
-from nmigen import *
-from nmigen.hdl.rec import *
+from nmigen import Elaboratable, Module, Mux, Record, Signal,
+from nmigen.hdl.rec import DIR_FANIN, DIR_FANOUT, DIR_NONE
 
 
 __all__ = ["Stage"]