From: Kevin Lim <ktlim@umich.edu>
Date: Tue, 10 Oct 2006 02:59:56 +0000 (-0400)
Subject: Merge ktlim@zizzer:/bk/newmem
X-Git-Tag: m5_2.0_beta2~104^2~24
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bdde892d668e17fb5a67de0e560a85b9092adf9e;p=gem5.git

Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem

src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/cpu/simple/timing.hh:
tests/configs/o3-timing-mp.py:
    Hand merge.

--HG--
extra : convert_revision : a58cc439eb5e8f900d175ed8b5a85b6c8723e558
---

bdde892d668e17fb5a67de0e560a85b9092adf9e
diff --cc src/cpu/o3/lsq_unit_impl.hh
index dc1a99d87,63ffcece1..3f9db912f
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@@ -608,13 -608,13 +608,13 @@@ LSQUnit<Impl>::writebackStores(
  
          DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
                  "to Addr:%#x, data:%#x [sn:%lli]\n",
 -                storeWBIdx, storeQueue[storeWBIdx].inst->readPC(),
 +                storeWBIdx, inst->readPC(),
                  req->getPaddr(), *(inst->memData),
 -                storeQueue[storeWBIdx].inst->seqNum);
 +                inst->seqNum);
  
          // @todo: Remove this SC hack once the memory system handles it.
-         if (req->getFlags() & LOCKED) {
-             if (req->getFlags() & UNCACHEABLE) {
+         if (req->isLocked()) {
+             if (req->isUncacheable()) {
                  req->setScResult(2);
              } else {
                  if (cpu->lockFlag) {
diff --cc src/cpu/simple/timing.hh
index 8a20d1cfe,18e13aeb2..988ddeded
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@@ -166,7 -166,7 +166,8 @@@ class TimingSimpleCPU : public BaseSimp
      Packet *ifetch_pkt;
      Packet *dcache_pkt;
  
+     int cpu_id;
 +    Tick previousTick;
  
    public:
  
diff --cc src/mem/physical.cc
index 0580954de,96d78bd99..7303f278e
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@@ -113,10 -195,12 +195,12 @@@ PhysicalMemory::checkLockedAddrList(Req
  void
  PhysicalMemory::doFunctionalAccess(Packet *pkt)
  {
 -    assert(pkt->getAddr() + pkt->getSize() < params()->addrRange.size());
 +    assert(pkt->getAddr() + pkt->getSize() <= params()->addrRange.size());
  
-     switch (pkt->cmd) {
-       case Packet::ReadReq:
+     if (pkt->isRead()) {
+         if (pkt->req->isLocked()) {
+             trackLoadLocked(pkt->req);
+         }
          memcpy(pkt->getPtr<uint8_t>(),
                 pmemAddr + pkt->getAddr() - params()->addrRange.start,
                 pkt->getSize());
diff --cc tests/configs/o3-timing-mp.py
index 09935d574,55af8be0d..68631b3d2
--- a/tests/configs/o3-timing-mp.py
+++ b/tests/configs/o3-timing-mp.py
@@@ -53,7 -54,7 +53,7 @@@ class L2(BaseCache)
      write_buffers = 8
  
  nb_cores = 4
- cpus = [ DerivO3CPU() for i in xrange(nb_cores) ]
 -cpus = [ DetailedO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
++cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
  
  # system simulated
  system = System(cpu = cpus, physmem = PhysicalMemory(), membus =