From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 7 Jun 2020 12:26:58 +0000 (+0100)
Subject: add missing arg to ISA in test_compunit
X-Git-Tag: div_pipeline~505
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bdf6ae1b6caf8ae21c563ac299bcf7250fd9a148;p=soc.git

add missing arg to ISA in test_compunit
---

diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py
index 67e7025f..42bfad75 100644
--- a/src/soc/fu/compunits/test/test_compunit.py
+++ b/src/soc/fu/compunits/test/test_compunit.py
@@ -142,7 +142,8 @@ class TestRunner(FHDLTestCase):
                 program = test.program
                 self.subTest(test.name)
                 print ("test", test.name, test.mem)
-                sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem)
+                sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem,
+                          test.msr)
                 gen = program.generate_instructions()
                 instructions = list(zip(gen, program.assembly.splitlines()))