From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Mon, 25 Jan 2021 13:24:28 +0000 (+0000)
Subject: arch-arm: Fix CPTR_EL2 writes
X-Git-Tag: develop-gem5-snapshot~94
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=be08e29991f6caab3b3853180a6fde11b14585c4;p=gem5.git

arch-arm: Fix CPTR_EL2 writes

* If E2H==1, CPTR_EL2.ZEN bits are not RES0.
* If E2H==1, CPTR_EL2.FPEN bits are not RES0.

Change-Id: Ic82b266975d89056d7c2f55464bd8a0c18a43e03
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39702
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 2429e5cb0..447eb6077 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -936,6 +936,7 @@ ISA::setMiscReg(int misc_reg, RegVal val)
             break;
           case MISCREG_CPTR_EL2:
             {
+                const HCR hcr = readMiscRegNoEffect(MISCREG_HCR_EL2);
                 const uint32_t ones = (uint32_t)(-1);
                 CPTR cptrMask = 0;
                 cptrMask.tcpac = ones;
@@ -943,7 +944,9 @@ ISA::setMiscReg(int misc_reg, RegVal val)
                 cptrMask.tfp = ones;
                 if (haveSVE) {
                     cptrMask.tz = ones;
+                    cptrMask.zen = hcr.e2h ? ones : 0;
                 }
+                cptrMask.fpen = hcr.e2h ? ones : 0;
                 newVal &= cptrMask;
                 cptrMask = 0;
                 cptrMask.res1_13_12_el2 = ones;