From: lkcl <lkcl@web>
Date: Sat, 11 Sep 2021 15:26:39 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~157
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=be1984326f91e54f5c6ab3378038600f9f042679;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index bc52f0af7..86d1589eb 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -116,6 +116,10 @@ unaffected by their SVP64 variants in every conceivable way.
 
 # Format and fields
 
+With element-width overrides being meaningless for Condition
+Register Fields, bits 4 thru 7 of SVP64 RM may be used for additional
+Mode bits.
+
 SVP64 RM `MODE` (includes `ELWIDTH` and `ELWIDTH_SRC` bits) for Branch
 Conditional: