From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 7 Nov 2018 09:20:42 +0000 (+0000)
Subject: attempting to get rv32 mv working
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=be46ee5337150b4e578a97485ee02868f8948278;p=riscv-isa-sim.git

attempting to get rv32 mv working
---

diff --git a/id_regs.py b/id_regs.py
index 03e255d..a1fdf67 100644
--- a/id_regs.py
+++ b/id_regs.py
@@ -95,12 +95,12 @@ def find_registers(fname, insn, twin_predication, immed_offset, is_branch):
                 src_flen = 128
                 dest_flen = 128
             if split[1].startswith('w'):
-                src_flen = 32
+                dest_flen = 32
             elif split[1].startswith('d'):
-                src_flen = 64
+                dest_flen = 64
             elif split[1].startswith('q'):
-                src_flen = 128
-        elif "f128(" in f:
+                dest_flen = 128
+        if "f128(" in f:
             src_flen = 128
             dest_flen = 128
         elif "f64(" in f or insn == 'fsd':