From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 4 May 2020 17:27:23 +0000 (+0100)
Subject: add links to bugreport and to memory/cache wiki page
X-Git-Tag: div_pipeline~1390
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=be5b74c3e28e0738620f68d9574c2f2f26e98a37;p=soc.git

add links to bugreport and to memory/cache wiki page
---

diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py
index 27e2af66..22168267 100644
--- a/src/soc/experiment/l0_cache.py
+++ b/src/soc/experiment/l0_cache.py
@@ -8,6 +8,11 @@ test infrastructure, and, just as with minerva's memory arrangement,
 a dynamic runtime config *selects* alternative memory arrangements
 rather than *replaces and discards* this code.
 
+Links:
+
+* https://bugs.libre-soc.org/show_bug.cgi?id=216
+* https://libre-soc.org/3d_gpu/architecture/memory_and_cache/
+
 """
 
 from nmigen.compat.sim import run_simulation