From: lkcl <lkcl@web>
Date: Sat, 30 Apr 2022 06:02:34 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2542
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=be66a397b3485c9d151440a7e487a359cd9ebdf3;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 493fb3f24..06e2a4aa8 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -959,6 +959,15 @@ more operands than would normally be seen in another ISA. If it
 was not for Power ISA already having LD/ST with update as well as
 Condition Codes and `lq` this would be hard to justify.
 
+With limited space in the `EXTRA` Field, and Power ISA opcodes
+being only 32 bit, 5 operands is quite an ask.  `lq` however sets
+a precedent: `RTp` stands for "RT pair".  In other words the result
+is stored in RT and RT+1.  For Scalar operations, following this
+precedent is perfectly reasonable.  In Scalar mode,
+`umadded` therefore stores the two halves of the 128-bit multiply
+into RT and RT+1.
+
+
 * [[isa/svfixedarith]]
 * [[isa/svfparith]]