From: Andrew Reynolds <andrew.j.reynolds@gmail.com>
Date: Wed, 15 Apr 2020 01:54:54 +0000 (-0500)
Subject: Disable preregistration of instantiations for cegqi in incremental (#4251)
X-Git-Tag: cvc5-1.0.0~3373
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=be6719144c88921fa39823976376961fe03f17a7;p=cvc5.git

Disable preregistration of instantiations for cegqi in incremental (#4251)

Fixes #4243.
---

diff --git a/src/smt/set_defaults.cpp b/src/smt/set_defaults.cpp
index 1384a2848..844d25379 100644
--- a/src/smt/set_defaults.cpp
+++ b/src/smt/set_defaults.cpp
@@ -1118,6 +1118,7 @@ void setDefaults(SmtEngine& smte, LogicInfo& logic)
     {
       // cannot do nested quantifier elimination in incremental mode
       options::cbqiNestedQE.set(false);
+      options::cbqiPreRegInst.set(false);
     }
     if (logic.isPure(THEORY_ARITH) || logic.isPure(THEORY_BV))
     {
diff --git a/test/regress/CMakeLists.txt b/test/regress/CMakeLists.txt
index 9608791f2..3c104862f 100644
--- a/test/regress/CMakeLists.txt
+++ b/test/regress/CMakeLists.txt
@@ -1519,6 +1519,7 @@ set(regress_1_tests
   regress1/quantifiers/issue3765-quant-dd.smt2
   regress1/quantifiers/issue4021-ind-opts.smt2
   regress1/quantifiers/issue4062-cegqi-aux.smt2
+  regress1/quantifiers/issue4243-prereg-inc.smt2
   regress1/quantifiers/issue4290-cegqi-r.smt2
   regress1/quantifiers/issue993.smt2
   regress1/quantifiers/javafe.ast.StmtVec.009.smt2
diff --git a/test/regress/regress1/quantifiers/issue4243-prereg-inc.smt2 b/test/regress/regress1/quantifiers/issue4243-prereg-inc.smt2
new file mode 100644
index 000000000..aa5cbc31e
--- /dev/null
+++ b/test/regress/regress1/quantifiers/issue4243-prereg-inc.smt2
@@ -0,0 +1,15 @@
+; COMMAND-LINE: -i
+; EXPECT: sat
+(set-logic BV)
+(set-info :status sat)
+(declare-fun _substvar_16_ () Bool)
+(set-option :cbqi-prereg-inst true)
+(set-option :check-models true)
+(declare-fun v2 () Bool)
+(push 1)
+(assert (exists ((q1 (_ BitVec 12)) (q2 Bool) (q3 (_ BitVec 12))) (xor _substvar_16_ q2 v2)))
+(push 1)
+(pop 1)
+(pop 1)
+(assert (forall ((q23 (_ BitVec 6))) v2))
+(check-sat)