From: Cesar Strauss <cestrauss@gmail.com>
Date: Tue, 2 Jun 2020 09:21:50 +0000 (-0300)
Subject: Hold rdmaskn active during the busy_o cycle
X-Git-Tag: div_pipeline~661
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=be756419825ec910c7bb29b6b1edc5586a4c506a;p=soc.git

Hold rdmaskn active during the busy_o cycle
---

diff --git a/src/soc/experiment/test/test_compalu_multi.py b/src/soc/experiment/test/test_compalu_multi.py
index ad70a1ec..95e8f3c5 100644
--- a/src/soc/experiment/test/test_compalu_multi.py
+++ b/src/soc/experiment/test/test_compalu_multi.py
@@ -198,12 +198,13 @@ class CompUnitParallelTest:
 
         # deactivate inputs along with issue_i, so we can be sure the data
         # was latched at the correct cycle
+        # note: rdmaskn must be held, while busy_o is active
+        # TODO: deactivate rdmaskn when the busy_o cycle ends
         yield self.dut.oper_i.insn_type.eq(0)
         yield self.dut.oper_i.invert_a.eq(0)
         yield self.dut.oper_i.imm_data.imm.eq(0)
         yield self.dut.oper_i.imm_data.imm_ok.eq(0)
         yield self.dut.oper_i.zero_a.eq(0)
-        yield self.dut.rdmaskn.eq(0)
         yield
 
         # wait for busy_o to lower