From: Michael Nolan <mtnolan2640@gmail.com>
Date: Fri, 15 May 2020 20:12:16 +0000 (-0400)
Subject: Implement op_bcreg
X-Git-Tag: div_pipeline~1161
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=be8d26fcf524b0b73d4980afd72228dc310cbec3;p=soc.git

Implement op_bcreg
---

diff --git a/src/soc/branch/main_stage.py b/src/soc/branch/main_stage.py
index 7d21be6a..b2cbc37a 100644
--- a/src/soc/branch/main_stage.py
+++ b/src/soc/branch/main_stage.py
@@ -100,7 +100,9 @@ class BranchMainStage(PipeModBase):
                 comb += br_imm_addr.eq(br_ext(bd))
                 comb += br_taken.eq(bc_taken)
             #### branch conditional reg ####
-            # TODOwith m.Case(InternalOp.OP_BCREG):
+            with m.Case(InternalOp.OP_BCREG):
+                comb += br_imm_addr.eq(self.i.spr)
+                comb += br_taken.eq(bc_taken)
 
         ###### output next instruction address #####