From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 19:39:11 +0000 (-0700)
Subject: Use abc_{map,unmap,model}.v
X-Git-Tag: working-ls180~881^2^2~232
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=be9e4f1b674ef4fb3f02e99efcfda04ea27b2a68;p=yosys.git

Use abc_{map,unmap,model}.v
---

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index cb4ec6183..7a467b91e 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -731,28 +731,21 @@ void AigerReader::parse_aiger_binary()
 
 void AigerReader::post_process()
 {
-	const RTLIL::Wire* n0 = module->wire("\\__0__");
-	const RTLIL::Wire* n1 = module->wire("\\__1__");
-
 	pool<IdString> seen_boxes;
-	dict<IdString, RTLIL::Module*> flop_data;
+	pool<IdString> flops;
 	unsigned ci_count = 0, co_count = 0, flop_count = 0;
 	for (auto cell : boxes) {
 		RTLIL::Module* box_module = design->module(cell->type);
 		log_assert(box_module);
 
-		RTLIL::Module* flop_module = nullptr;
+		bool is_flop = false;
 		if (seen_boxes.insert(cell->type).second) {
-			auto it = box_module->attributes.find("\\abc_flop");
-			if (it != box_module->attributes.end()) {
+			if (box_module->attributes.count("\\abc_flop")) {
 				log_assert(flop_count < flopNum);
-				auto abc_flop = it->second.decode_string();
-				flop_module = design->module(RTLIL::escape_id(abc_flop));
-				if (!flop_module)
-					log_error("'abc_flop' attribute value '%s' on module '%s' is not a valid module.\n", abc_flop.c_str(), log_id(cell->type));
-				flop_data[cell->type] = flop_module;
+				flops.insert(cell->type);
+				is_flop = true;
 			}
-			it = box_module->attributes.find("\\abc_carry");
+			auto it = box_module->attributes.find("\\abc_carry");
 			if (it != box_module->attributes.end()) {
 				RTLIL::Wire *carry_in = nullptr, *carry_out = nullptr;
 				auto carry_in_out = it->second.decode_string();
@@ -791,11 +784,8 @@ void AigerReader::post_process()
 				carry_out->port_id = ports.size();
 			}
 		}
-		else {
-			auto it = flop_data.find(cell->type);
-			if (it != flop_data.end())
-				flop_module = it->second;
-		}
+		else
+			is_flop = flops.count(cell->type);
 
 		// NB: Assume box_module->ports are sorted alphabetically
 		//     (as RTLIL::Module::fixup_ports() would do)
@@ -822,11 +812,11 @@ void AigerReader::post_process()
 				rhs.append(wire);
 			}
 
-			if (!flop_module || port_name != "\\$pastQ")
+			if (!is_flop || port_name != "\\$pastQ")
 				cell->setPort(port_name, rhs);
 		}
 
-		if (flop_module) {
+		if (is_flop) {
 			RTLIL::Wire *d = outputs[outputs.size() - flopNum + flop_count];
 			log_assert(d);
 			log_assert(d->port_output);
@@ -838,21 +828,10 @@ void AigerReader::post_process()
 			q->port_input = false;
 
 			flop_count++;
-			cell->type = flop_module->name;
 			module->connect(q, d);
 			cell->set_bool_attribute("\\abc_flop");
 			continue;
 		}
-
-		// Remove the async mux by shorting out its input and output
-		if (cell->type == "$__ABC_ASYNC") {
-			RTLIL::Wire* A = cell->getPort("\\A").as_wire();
-			if (A == n0 || A == n1) A = nullptr;
-			auto it = cell->connections_.find("\\Y");
-			log_assert(it != cell->connections_.end());
-			module->connect(it->second, A);
-			cell->connections_.erase(it);
-		}
 	}
 
 	dict<RTLIL::IdString, int> wideports_cache;
diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc
index a9e0c5c7b..a11880c4d 100644
--- a/techlibs/xilinx/Makefile.inc
+++ b/techlibs/xilinx/Makefile.inc
@@ -39,7 +39,9 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v))
 
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_ff.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_map.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_unmap.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_model.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.box))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.lut))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7_nowide.lut))
diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
deleted file mode 100644
index 36e1a08e4..000000000
--- a/techlibs/xilinx/abc_ff.v
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- *  yosys -- Yosys Open SYnthesis Suite
- *
- *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *                2019  Eddie Hung    <eddie@fpgeh.com>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-// ============================================================================
-
-// Max delays from https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251
-
-module FDRE (output reg Q, input C, CE, D, R);
-  parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_R_INVERTED = 1'b0;
-  wire \$nextQ ;
-  \$__ABC_FDRE #(
-    .INIT(INIT),
-    .IS_C_INVERTED(IS_C_INVERTED),
-    .IS_D_INVERTED(IS_D_INVERTED),
-    .IS_R_INVERTED(IS_R_INVERTED)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R)
-  );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
-endmodule
-module FDRE_1 (output reg Q, input C, CE, D, R);
-  parameter [0:0] INIT = 1'b0;
-  wire \$nextQ ;
-  \$__ABC_FDRE_1 #(.INIT(|0)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R)
-  );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
-endmodule
-
-module FDCE (output reg Q, input C, CE, D, CLR);
-  parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_CLR_INVERTED = 1'b0;
-  wire \$nextQ , \$currQ ;
-  \$__ABC_FDCE #(
-    .INIT(INIT),
-    .IS_C_INVERTED(IS_C_INVERTED),
-    .IS_D_INVERTED(IS_D_INVERTED),
-    .IS_CLR_INVERTED(IS_CLR_INVERTED)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
-  );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
-  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q));
-endmodule
-module FDCE_1 (output reg Q, input C, CE, D, CLR);
-  parameter [0:0] INIT = 1'b0;
-  wire \$nextQ , \$currQ ;
-  \$__ABC_FDCE_1 #(
-    .INIT(INIT)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
-  );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
-  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q));
-endmodule
-
-module FDPE (output reg Q, input C, CE, D, PRE);
-  parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_PRE_INVERTED = 1'b0;
-  wire \$nextQ , \$currQ ;
-  \$__ABC_FDPE #(
-    .INIT(INIT),
-    .IS_C_INVERTED(IS_C_INVERTED),
-    .IS_D_INVERTED(IS_D_INVERTED),
-    .IS_PRE_INVERTED(IS_PRE_INVERTED)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
-  );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
-  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
-endmodule
-module FDPE_1 (output reg Q, input C, CE, D, PRE);
-  parameter [0:0] INIT = 1'b0;
-  wire \$nextQ , \$currQ ;
-  \$__ABC_FDPE_1 #(
-    .INIT(INIT)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
-  );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
-  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
-endmodule
-
-`ifndef _ABC
-module \$__ABC_FF_ (input C, D, output Q);
-endmodule
-
-(* abc_box_id = 1000 *)
-module \$__ABC_ASYNC (input A, S, output Y);
-endmodule
-
-(* abc_box_id=1001, lib_whitebox, abc_flop="FDRE", abc_flop_clk_pol="!IS_C_INVERTED", abc_flop_en_pol=1 *)
-module \$__ABC_FDRE ((* abc_flop_q, abc_arrival=303 *) output Q,
-                     (* abc_flop_clk *) input C,
-                     (* abc_flop_en *)  input CE,
-                     (* abc_flop_d *)   input D,
-                     input R, \$pastQ );
-  parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_R_INVERTED = 1'b0;
-  assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
-endmodule
-
-(* abc_box_id = 1002, lib_whitebox, abc_flop = "FDRE_1", abc_flop_clk_pol=1, abc_flop_en_pol=1 *)
-module \$__ABC_FDRE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
-                       (* abc_flop_clk *) input C,
-                       (* abc_flop_en *)  input CE,
-                       (* abc_flop_d *)   input D,
-                       input R, \$pastQ );
-  parameter [0:0] INIT = 1'b0;
-  assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
-endmodule
-
-(* abc_box_id = 1003, lib_whitebox, abc_flop = "FDCE", abc_flop_clk_pol="!IS_C_INVERTED", abc_flop_en_pol=1 *)
-module \$__ABC_FDCE ((* abc_flop_q, abc_arrival=303 *) output Q,
-                     (* abc_flop_clk *) input C,
-                     (* abc_flop_en *)  input CE,
-                     (* abc_flop_d *)   input D,
-                     input CLR, \$pastQ );
-  parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_CLR_INVERTED = 1'b0;
-  assign Q = (CE && !(CLR ^ IS_CLR_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
-endmodule
-
-(* abc_box_id = 1004, lib_whitebox, abc_flop = "FDCE_1", abc_flop_clk_pol=1, abc_flop_en_pol=1 *)
-module \$__ABC_FDCE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
-                       (* abc_flop_clk *) input C,
-                       (* abc_flop_en *)  input CE,
-                       (* abc_flop_d *)   input D,
-                       input CLR, \$pastQ );
-  parameter [0:0] INIT = 1'b0;
-  assign Q = (CE && !CLR) ? D : \$pastQ ;
-endmodule
-
-(* abc_box_id=1005, lib_whitebox, abc_flop="FDPE", abc_flop_clk_pol="!IS_C_INVERTED", abc_flop_en_pol=1 *)
-module \$__ABC_FDPE ((* abc_flop_q, abc_arrival=303 *) output Q,
-                     (* abc_flop_clk *) input C,
-                     (* abc_flop_en *)  input CE,
-                     (* abc_flop_d *)   input D,
-                     input PRE, \$pastQ );
-  parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_PRE_INVERTED = 1'b0;
-  assign Q = (CE && !(PRE ^ IS_PRE_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
-endmodule
-
-(* abc_box_id=1006, lib_whitebox, abc_flop="FDPE_1", abc_flop_clk_pol=1, abc_flop_en_pol=1 *)
-module \$__ABC_FDPE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
-                       (* abc_flop_clk *) input C,
-                       (* abc_flop_en *)  input CE,
-                       (* abc_flop_d *)   input D,
-                       input PRE, \$pastQ );
-  parameter [0:0] INIT = 1'b0;
-  assign Q = (CE && !PRE) ? D : \$pastQ ;
-endmodule
-
-`endif
diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
new file mode 100644
index 000000000..99e1fe127
--- /dev/null
+++ b/techlibs/xilinx/abc_map.v
@@ -0,0 +1,120 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *                2019  Eddie Hung    <eddie@fpgeh.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+// ============================================================================
+
+// Max delays from https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251
+
+module FDRE (output reg Q, input C, CE, D, R);
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_R_INVERTED = 1'b0;
+  wire \$nextQ ;
+  \$__ABC_FDRE #(
+    .INIT(INIT),
+    .IS_C_INVERTED(IS_C_INVERTED),
+    .IS_D_INVERTED(IS_D_INVERTED),
+    .IS_R_INVERTED(IS_R_INVERTED),
+    .CLK_POLARITY(!IS_C_INVERTED),
+    .EN_POLARITY(1'b1)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R)
+  );
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+endmodule
+module FDRE_1 (output reg Q, input C, CE, D, R);
+  parameter [0:0] INIT = 1'b0;
+  wire \$nextQ ;
+  \$__ABC_FDRE_1 #(
+      .INIT(|0),
+    .CLK_POLARITY(1'b0),
+    .EN_POLARITY(1'b1)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R)
+  );
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+endmodule
+
+module FDCE (output reg Q, input C, CE, D, CLR);
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_CLR_INVERTED = 1'b0;
+  wire \$nextQ , \$currQ ;
+  \$__ABC_FDCE #(
+    .INIT(INIT),
+    .IS_C_INVERTED(IS_C_INVERTED),
+    .IS_D_INVERTED(IS_D_INVERTED),
+    .IS_CLR_INVERTED(IS_CLR_INVERTED),
+    .CLK_POLARITY(!IS_C_INVERTED),
+    .EN_POLARITY(1'b1)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
+  );
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
+  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q));
+endmodule
+module FDCE_1 (output reg Q, input C, CE, D, CLR);
+  parameter [0:0] INIT = 1'b0;
+  wire \$nextQ , \$currQ ;
+  \$__ABC_FDCE_1 #(
+    .INIT(INIT),
+    .CLK_POLARITY(1'b0),
+    .EN_POLARITY(1'b1)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
+  );
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
+  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q));
+endmodule
+
+module FDPE (output reg Q, input C, CE, D, PRE);
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_PRE_INVERTED = 1'b0;
+  wire \$nextQ , \$currQ ;
+  \$__ABC_FDPE #(
+    .INIT(INIT),
+    .IS_C_INVERTED(IS_C_INVERTED),
+    .IS_D_INVERTED(IS_D_INVERTED),
+    .IS_PRE_INVERTED(IS_PRE_INVERTED),
+    .CLK_POLARITY(!IS_C_INVERTED),
+    .EN_POLARITY(1'b1)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
+  );
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
+  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
+endmodule
+module FDPE_1 (output reg Q, input C, CE, D, PRE);
+  parameter [0:0] INIT = 1'b0;
+  wire \$nextQ , \$currQ ;
+  \$__ABC_FDPE_1 #(
+    .INIT(INIT),
+    .CLK_POLARITY(1'b0),
+    .EN_POLARITY(1'b1)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
+  );
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
+  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
+endmodule
diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v
new file mode 100644
index 000000000..41c232650
--- /dev/null
+++ b/techlibs/xilinx/abc_model.v
@@ -0,0 +1,148 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *                2019  Eddie Hung    <eddie@fpgeh.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+// ============================================================================
+
+(* abc_box_id = 3, lib_whitebox *)
+module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
+  assign O = S1 ? (S0 ? I3 : I2)
+                : (S0 ? I1 : I0);
+endmodule
+
+module \$__ABC_FF_ (input C, D, output Q);
+endmodule
+
+(* abc_box_id = 1000 *)
+module \$__ABC_ASYNC (input A, S, output Y);
+endmodule
+
+(* abc_box_id=1001, lib_whitebox, abc_flop *)
+module \$__ABC_FDRE ((* abc_flop_q, abc_arrival=303 *) output Q,
+                     (* abc_flop_clk *) input C,
+                     (* abc_flop_en *)  input CE,
+                     (* abc_flop_d *)   input D,
+                     input R, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_R_INVERTED = 1'b0;
+  parameter CLK_POLARITY = !IS_C_INVERTED;
+  parameter EN_POLARITY = 1'b1;
+  assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
+endmodule
+
+(* abc_box_id=1002, lib_whitebox, abc_flop *)
+module \$__ABC_FDRE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
+                       (* abc_flop_clk *) input C,
+                       (* abc_flop_en *)  input CE,
+                       (* abc_flop_d *)   input D,
+                       input R, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter CLK_POLARITY = 1'b0;
+  parameter EN_POLARITY = 1'b1;
+  assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
+endmodule
+
+(* abc_box_id=1003, lib_whitebox, abc_flop *)
+module \$__ABC_FDCE ((* abc_flop_q, abc_arrival=303 *) output Q,
+                     (* abc_flop_clk *) input C,
+                     (* abc_flop_en *)  input CE,
+                     (* abc_flop_d *)   input D,
+                     input CLR, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_CLR_INVERTED = 1'b0;
+  parameter CLK_POLARITY = !IS_C_INVERTED;
+  parameter EN_POLARITY = 1'b1;
+  assign Q = (CE && !(CLR ^ IS_CLR_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
+endmodule
+
+(* abc_box_id=1004, lib_whitebox, abc_flop *)
+module \$__ABC_FDCE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
+                       (* abc_flop_clk *) input C,
+                       (* abc_flop_en *)  input CE,
+                       (* abc_flop_d *)   input D,
+                       input CLR, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter CLK_POLARITY = 1'b0;
+  parameter EN_POLARITY = 1'b1;
+  assign Q = (CE && !CLR) ? D : \$pastQ ;
+endmodule
+
+(* abc_box_id=1005, lib_whitebox, abc_flop *)
+module \$__ABC_FDPE ((* abc_flop_q, abc_arrival=303 *) output Q,
+                     (* abc_flop_clk *) input C,
+                     (* abc_flop_en *)  input CE,
+                     (* abc_flop_d *)   input D,
+                     input PRE, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_PRE_INVERTED = 1'b0;
+  parameter CLK_POLARITY = !IS_C_INVERTED;
+  parameter EN_POLARITY = 1'b1;
+  assign Q = (CE && !(PRE ^ IS_PRE_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
+endmodule
+
+(* abc_box_id=1006, lib_whitebox, abc_flop *)
+module \$__ABC_FDPE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
+                       (* abc_flop_clk *) input C,
+                       (* abc_flop_en *)  input CE,
+                       (* abc_flop_d *)   input D,
+                       input PRE, \$pastQ );
+  parameter [0:0] INIT = 1'b0; 
+  parameter CLK_POLARITY = 1'b0;
+  parameter EN_POLARITY = 1'b1;
+  assign Q = (CE && !PRE) ? D : \$pastQ ;
+endmodule
+
+module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1);
+  output O;
+  input I0, I1, I2, I3, S0, S1;
+  wire T0, T1;
+  parameter _TECHMAP_BITS_CONNMAP_ = 0;
+  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I0_ = 0;
+  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I1_ = 0;
+  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I2_ = 0;
+  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I3_ = 0;
+  parameter _TECHMAP_CONSTMSK_S0_ = 0;
+  parameter _TECHMAP_CONSTVAL_S0_ = 0;
+  parameter _TECHMAP_CONSTMSK_S1_ = 0;
+  parameter _TECHMAP_CONSTVAL_S1_ = 0;
+  if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)
+    assign T0 = I1;
+  else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_)
+    assign T0 = I0;
+  else
+    MUXF7 mux7a (.I0(I0), .I1(I1), .S(S0), .O(T0));
+  if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)
+    assign T1 = I3;
+  else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_)
+    assign T1 = I2;
+  else
+    MUXF7 mux7b (.I0(I2), .I1(I3), .S(S0), .O(T1));
+  if (_TECHMAP_CONSTMSK_S1_ && _TECHMAP_CONSTVAL_S1_ === 1'b1)
+    assign O = T1;
+  else if (_TECHMAP_CONSTMSK_S1_ || (_TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_ && _TECHMAP_CONNMAP_I1_ === _TECHMAP_CONNMAP_I2_ && _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_))
+    assign O = T0;
+  else
+    MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O));
+endmodule
diff --git a/techlibs/xilinx/abc_unmap.v b/techlibs/xilinx/abc_unmap.v
new file mode 100644
index 000000000..6de766e76
--- /dev/null
+++ b/techlibs/xilinx/abc_unmap.v
@@ -0,0 +1,140 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *                2019  Eddie Hung    <eddie@fpgeh.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+// ============================================================================
+
+module \$__ABC_ASYNC (input A, S, output Y);
+  assign Y = A;
+endmodule
+
+module \$__ABC_FDRE (output Q,
+                     input C,
+                     input CE,
+                     input D,
+                     input R, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_R_INVERTED = 1'b0;
+  parameter CLK_POLARITY = !IS_C_INVERTED;
+  parameter EN_POLARITY = 1'b1;
+
+  FDRE #(
+    .INIT(INIT),
+    .IS_C_INVERTED(IS_C_INVERTED),
+    .IS_D_INVERTED(IS_D_INVERTED),
+    .IS_R_INVERTED(IS_R_INVERTED),
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(Q), .C(C), .CE(CE), .R(R)
+  );
+endmodule
+
+module \$__ABC_FDRE_1 (output Q,
+                       input C,
+                       input CE,
+                       input D,
+                       input R, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter CLK_POLARITY = 1'b0;
+  parameter EN_POLARITY = 1'b1;
+  assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
+
+  FDRE_1 #(
+    .INIT(INIT),
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(Q), .C(C), .CE(CE), .R(R)
+  );
+endmodule
+
+module \$__ABC_FDCE (output Q,
+                     input C,
+                     input CE,
+                     input D,
+                     input CLR, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_CLR_INVERTED = 1'b0;
+  parameter CLK_POLARITY = !IS_C_INVERTED;
+  parameter EN_POLARITY = 1'b1;
+
+  FDCE #(
+    .INIT(INIT),
+    .IS_C_INVERTED(IS_C_INVERTED),
+    .IS_D_INVERTED(IS_D_INVERTED),
+    .IS_CLR_INVERTED(IS_CLR_INVERTED),
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
+  );
+endmodule
+
+module \$__ABC_FDCE_1 (output Q,
+                       input C,
+                       input CE,
+                       input D,
+                       input CLR, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter CLK_POLARITY = 1'b0;
+  parameter EN_POLARITY = 1'b1;
+
+  FDCE_1 #(
+    .INIT(INIT),
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
+  );
+endmodule
+
+module \$__ABC_FDPE (output Q,
+                     input C,
+                     input CE,
+                     input D,
+                     input PRE, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_PRE_INVERTED = 1'b0;
+  parameter CLK_POLARITY = !IS_C_INVERTED;
+  parameter EN_POLARITY = 1'b1;
+
+  FDPE #(
+    .INIT(INIT),
+    .IS_C_INVERTED(IS_C_INVERTED),
+    .IS_D_INVERTED(IS_D_INVERTED),
+    .IS_PRE_INVERTED(IS_PRE_INVERTED),
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
+  );
+endmodule
+
+module \$__ABC_FDPE_1 (output Q,
+                       input C,
+                       input CE,
+                       input D,
+                       input PRE, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter CLK_POLARITY = 1'b0;
+  parameter EN_POLARITY = 1'b1;
+
+  FDPE_1 #(
+    .INIT(INIT),
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
+  );
+endmodule
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index b8e5bafc7..a15884ec4 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -331,7 +331,6 @@ module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y)
 endmodule
 `endif
 
-`ifndef _ABC
 module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1);
   output O;
   input I0, I1, I2, I3, S0, S1;
@@ -364,4 +363,3 @@ module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1);
   else
     MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O));
 endmodule
-`endif
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index dd5a76752..614fd8eef 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -169,14 +169,6 @@ module MUXF8(output O, input I0, I1, S);
   assign O = S ? I1 : I0;
 endmodule
 
-`ifdef _ABC
-(* abc_box_id = 3, lib_whitebox *)
-module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
-  assign O = S1 ? (S0 ? I3 : I2)
-                : (S0 ? I1 : I0);
-endmodule
-`endif
-
 module XORCY(output O, input CI, LI);
   assign O = CI ^ LI;
 endmodule
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 6456dbdf4..3525e4de9 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -230,9 +230,9 @@ struct SynthXilinxPass : public ScriptPass
 	{
 		if (check_label("begin")) {
 			if (vpr)
-				run("read_verilog -lib -icells -D _ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
+				run("read_verilog -lib -icells -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
 			else
-				run("read_verilog -lib -icells -D _ABC +/xilinx/cells_sim.v");
+				run("read_verilog -lib -icells +/xilinx/cells_sim.v");
 
 			run("read_verilog -lib +/xilinx/cells_xtra.v");
 
@@ -373,11 +373,11 @@ struct SynthXilinxPass : public ScriptPass
 		}
 
 		if (check_label("map_cells")) {
-			std::string techmap_args = "-map +/techmap.v -D _ABC -map +/xilinx/cells_map.v";
+			std::string techmap_args = "-map +/techmap.v -map +/xilinx/cells_map.v";
 			if (widemux > 0)
 				techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);
 			if (abc9)
-				techmap_args += " -map +/xilinx/ff_map.v -D _ABC -map +/xilinx/abc_ff.v";
+				techmap_args += " -map +/xilinx/ff_map.v -map +/xilinx/abc_map.v";
 			run("techmap " + techmap_args);
 			run("clean");
 		}
@@ -389,7 +389,7 @@ struct SynthXilinxPass : public ScriptPass
 			else if (abc9) {
 				if (family != "xc7")
 					log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
-				run("read_verilog -icells -lib +/xilinx/abc_ff.v");
+				run("read_verilog -icells -lib +/xilinx/abc_model.v");
 				if (nowidelut)
 					run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
 				else
@@ -408,7 +408,7 @@ struct SynthXilinxPass : public ScriptPass
 			if (!nosrl || help_mode)
 				run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
 			if (abc9)
-				run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v");
+				run("techmap -map +/xilinx/lut_map.v -map +/xilinx/abc_unmap.v");
 			else
 				run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v");
 			run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "