From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 2 May 2021 10:39:48 +0000 (+0100)
Subject: quick hack to SRAM test and to dcache to enable classic wishbone
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=be9e889729a3a0d9650dbb9d0b5931710d3bc10c;p=soc.git

quick hack to SRAM test and to dcache to enable classic wishbone
---

diff --git a/src/soc/bus/sram.py b/src/soc/bus/sram.py
index 7d634909..9819302f 100644
--- a/src/soc/bus/sram.py
+++ b/src/soc/bus/sram.py
@@ -99,7 +99,7 @@ class SRAM(Elaboratable):
 
         # generate ack (no "pipeline" mode here)
         m.d.sync += self.bus.ack.eq(0)
-        with m.If(self.bus.cyc & self.bus.stb):
+        with m.If(self.bus.cyc & self.bus.stb & ~self.bus.ack):
             m.d.sync += self.bus.ack.eq(1)
 
         return m
diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index c8104301..7059cf83 100644
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -1652,7 +1652,7 @@ cache_tags(r1.store_index)((i + 1) * TAG_WIDTH - 1 downto i * TAG_WIDTH) <=
         # deal with litex not doing wishbone pipeline mode
         # XXX in wrong way.  FIFOs are needed in the SRAM test
         # so that stb/ack match up
-        #comb += self.wb_in.stall.eq(self.wb_out.cyc & ~self.wb_in.ack)
+        comb += self.wb_in.stall.eq(self.wb_out.cyc & ~self.wb_in.ack)
 
         # call sub-functions putting everything together, using shared
         # signals established above