From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Thu, 4 Feb 2016 07:38:29 +0000 (-0800)
Subject: Actually refill ITLB on ITLB miss
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bea283531abfd013811e83c75ff6189a0d9b3075;p=riscv-isa-sim.git

Actually refill ITLB on ITLB miss

oops.
---

diff --git a/riscv/mmu.cc b/riscv/mmu.cc
index 4558b1e..0073a8a 100644
--- a/riscv/mmu.cc
+++ b/riscv/mmu.cc
@@ -50,7 +50,9 @@ reg_t mmu_t::translate(reg_t addr, access_type type)
 const uint16_t* mmu_t::fetch_slow_path(reg_t addr)
 {
   reg_t paddr = translate(addr, FETCH);
-  if (paddr >= memsz)
+  if (paddr < memsz)
+    refill_tlb(addr, paddr, FETCH);
+  else
     throw trap_instruction_access_fault(addr);
   return (const uint16_t*)(mem + paddr);
 }