From: Samuel Pitoiset Date: Thu, 6 Aug 2020 15:50:33 +0000 (+0200) Subject: radv: allow to force-enable LLVM internally for a specific shader stage X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bea8930468e18e3371e4457380232ec04bda4990;p=mesa.git radv: allow to force-enable LLVM internally for a specific shader stage For ACO debugging purposes, developers only. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: --- diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 57d1253effd..33d594f6c48 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -2625,7 +2625,7 @@ radv_fill_shader_info(struct radv_pipeline *pipeline, pipeline->layout, &keys[MESA_SHADER_FRAGMENT], &infos[MESA_SHADER_FRAGMENT], - pipeline->device->physical_device->use_llvm); + radv_use_llvm_for_stage(pipeline->device, MESA_SHADER_FRAGMENT)); /* TODO: These are no longer used as keys we should refactor this */ keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id = @@ -2677,7 +2677,7 @@ radv_fill_shader_info(struct radv_pipeline *pipeline, radv_nir_shader_info_pass(combined_nir[i], pipeline->layout, &key, &infos[MESA_SHADER_TESS_CTRL], - pipeline->device->physical_device->use_llvm); + radv_use_llvm_for_stage(pipeline->device, MESA_SHADER_TESS_CTRL)); } keys[MESA_SHADER_TESS_EVAL].tes.num_patches = @@ -2701,7 +2701,7 @@ radv_fill_shader_info(struct radv_pipeline *pipeline, pipeline->layout, &keys[pre_stage], &infos[MESA_SHADER_GEOMETRY], - pipeline->device->physical_device->use_llvm); + radv_use_llvm_for_stage(pipeline->device, MESA_SHADER_GEOMETRY)); } filled_stages |= (1 << pre_stage); @@ -2726,7 +2726,8 @@ radv_fill_shader_info(struct radv_pipeline *pipeline, radv_nir_shader_info_init(&infos[i]); radv_nir_shader_info_pass(nir[i], pipeline->layout, - &keys[i], &infos[i], pipeline->device->physical_device->use_llvm); + &keys[i], &infos[i], + radv_use_llvm_for_stage(pipeline->device, i)); } for (int i = 0; i < MESA_SHADER_STAGES; i++) { @@ -2936,7 +2937,7 @@ VkResult radv_create_shaders(struct radv_pipeline *pipeline, /* do this again since information such as outputs_read can be out-of-date */ nir_shader_gather_info(nir[i], nir_shader_get_entrypoint(nir[i])); - if (device->physical_device->use_llvm) { + if (radv_use_llvm_for_stage(device, i)) { NIR_PASS_V(nir[i], nir_lower_bool_to_int32); } else { NIR_PASS_V(nir[i], nir_lower_non_uniform_access, @@ -2994,7 +2995,8 @@ VkResult radv_create_shaders(struct radv_pipeline *pipeline, radv_nir_shader_info_pass(nir[MESA_SHADER_GEOMETRY], pipeline->layout, &key, - &info, pipeline->device->physical_device->use_llvm); + &info, + radv_use_llvm_for_stage(pipeline->device, MESA_SHADER_GEOMETRY)); info.wave_size = 64; /* Wave32 not supported. */ info.ballot_bit_size = 64; @@ -5513,7 +5515,7 @@ VkResult radv_GetPipelineExecutableInternalRepresentationsKHR( /* backend IR */ if (p < end) { p->isText = true; - if (pipeline->device->physical_device->use_llvm) { + if (radv_use_llvm_for_stage(pipeline->device, stage)) { desc_copy(p->name, "LLVM IR"); desc_copy(p->description, "The LLVM IR after some optimizations"); } else { diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 2fb36084a15..603b0c94a22 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -2604,6 +2604,16 @@ static inline uint32_t si_translate_stencil_op(enum VkStencilOp op) } } +/** + * Helper used for debugging compiler issues by enabling/disabling LLVM for a + * specific shader stage (developers only). + */ +static inline bool +radv_use_llvm_for_stage(struct radv_device *device, UNUSED gl_shader_stage stage) +{ + return device->physical_device->use_llvm; +} + #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \ \ static inline struct __radv_type * \ diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index f54b2e2a806..81680e548b5 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -311,8 +311,7 @@ radv_shader_compile_to_nir(struct radv_device *device, { nir_shader *nir; const nir_shader_compiler_options *nir_options = - device->physical_device->use_llvm ? &nir_options_llvm : - &nir_options_aco; + radv_use_llvm_for_stage(device, stage) ? &nir_options_llvm : &nir_options_aco; if (module->nir) { /* Some things such as our meta clear/blit code will give us a NIR @@ -464,7 +463,7 @@ radv_shader_compile_to_nir(struct radv_device *device, NIR_PASS_V(nir, nir_split_per_member_structs); if (nir->info.stage == MESA_SHADER_FRAGMENT && - !device->physical_device->use_llvm) + !radv_use_llvm_for_stage(device, nir->info.stage)) NIR_PASS_V(nir, nir_lower_io_to_vector, nir_var_shader_out); if (nir->info.stage == MESA_SHADER_FRAGMENT) NIR_PASS_V(nir, nir_lower_input_attachments, true); @@ -1170,11 +1169,11 @@ shader_variant_compile(struct radv_device *device, shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX); - if (device->physical_device->use_llvm || + if (radv_use_llvm_for_stage(device, stage) || options->dump_shader || options->record_ir) ac_init_llvm_once(); - if (device->physical_device->use_llvm) { + if (radv_use_llvm_for_stage(device, stage)) { llvm_compile_shader(device, shader_count, shaders, &binary, &args); } else { aco_compile_shader(shader_count, shaders, &binary, &args); @@ -1232,16 +1231,17 @@ radv_shader_variant_compile(struct radv_device *device, bool keep_shader_info, bool keep_statistic_info, struct radv_shader_binary **binary_out) { + gl_shader_stage stage = shaders[shader_count - 1]->info.stage; struct radv_nir_compiler_options options = {0}; options.layout = layout; if (key) options.key = *key; - options.explicit_scratch_args = !device->physical_device->use_llvm; + options.explicit_scratch_args = !radv_use_llvm_for_stage(device, stage); options.robust_buffer_access = device->robust_buffer_access; - return shader_variant_compile(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage, info, + return shader_variant_compile(device, module, shaders, shader_count, stage, info, &options, false, keep_shader_info, keep_statistic_info, binary_out); } @@ -1254,11 +1254,12 @@ radv_create_gs_copy_shader(struct radv_device *device, bool multiview) { struct radv_nir_compiler_options options = {0}; + gl_shader_stage stage = MESA_SHADER_VERTEX; - options.explicit_scratch_args = !device->physical_device->use_llvm; + options.explicit_scratch_args = !radv_use_llvm_for_stage(device, stage); options.key.has_multiview_view_index = multiview; - return shader_variant_compile(device, NULL, &shader, 1, MESA_SHADER_VERTEX, + return shader_variant_compile(device, NULL, &shader, 1, stage, info, &options, true, keep_shader_info, keep_statistic_info, binary_out); }