From: Kito Cheng <kito.cheng@sifive.com>
Date: Tue, 16 Jun 2020 02:14:13 +0000 (+0800)
Subject: RISC-V: Fix ICE on riscv_gpr_save_operation_p [PR95683]
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=beaf12b49ae030505194cdcac18b5c8533a43921;p=gcc.git

RISC-V: Fix ICE on riscv_gpr_save_operation_p [PR95683]

 - riscv_gpr_save_operation_p might try to match parallel on other
   patterns like inline asm pattern, and then it might trigger ther
   assertion checking there, so we could trun it into a early exit check.

gcc/ChangeLog:

	PR target/95683
	* config/riscv/riscv.c (riscv_gpr_save_operation_p): Remove
	assertion and turn it into a early exit check.

gcc/testsuite/ChangeLog

	PR target/95683
	* gcc.target/riscv/pr95683.c: New.
---

diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index 328c0c823a3..bfb3885ed08 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -5216,7 +5216,10 @@ bool
 riscv_gpr_save_operation_p (rtx op)
 {
   unsigned len = XVECLEN (op, 0);
-  gcc_assert (len <= ARRAY_SIZE (gpr_save_reg_order));
+
+  if (len > ARRAY_SIZE (gpr_save_reg_order))
+    return false;
+
   for (unsigned i = 0; i < len; i++)
     {
       rtx elt = XVECEXP (op, 0, i);
diff --git a/gcc/testsuite/gcc.target/riscv/pr95683.c b/gcc/testsuite/gcc.target/riscv/pr95683.c
new file mode 100644
index 00000000000..00cfbdcf282
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr95683.c
@@ -0,0 +1,10 @@
+/* PR target/95683 */
+/* { dg-options "-Os" } */
+/* { dg-do compile } */
+void a() {
+  asm(""
+      :
+      :
+      : "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
+        "t4", "t5", "t6", "ra");
+}