From: Luke Kenneth Casson Leighton Date: Mon, 29 Oct 2018 02:29:19 +0000 (+0000) Subject: add example illustrative tables X-Git-Tag: convert-csv-opcode-to-binary~4884 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=beb3c93c4cde39698aab21e8c56894855d4cd6c3;p=libreriscv.git add example illustrative tables --- diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index aaf546f7d..fa7681379 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -1551,10 +1551,11 @@ Note: LH - 16-bit load, to elwidth 32-bit -^ byte 0 ^ byte 1 ^ byte 2 ^ byte 3 ^ byte 4 ^ byte 5 ^ byte 6 ^ byte 7 ^ -| ------ | ------ | ------ | ------ | ------ | ------ | ------ | ------ | -| elem 0 || elem 1 || elem 2 || elem 3 || -| elem 4 || elem 5 || elem 6 || elem 7 || +| addr | byte 0 | byte 1 | byte 2 | byte 3 | byte 4 | byte 5 | byte 6 | byte 7 | +| ---- | ------ | ------ | ------ | ------ | ------ | ------ | ------ | ------ | +| @x5 | elem 0 || elem 1 || elem 2 || elem 3 || +| @x6 | elem 4 || elem 5 || elem 6 || elem 7 || +| .... | ...... | ...... | ...... | ...... | ...... | ...... | ...... | ...... | ## Why SV bitwidth specification is restricted to 4 entries