From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 1 Feb 2015 22:06:44 +0000 (+0100)
Subject: no support for 6-series xilinx devices
X-Git-Tag: yosys-0.5~34
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bebbf2e5a4ca6a1378f621243dfc06b185a6884e;p=yosys.git

no support for 6-series xilinx devices
---

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index caa7e205d..7812fa290 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -44,7 +44,7 @@ struct SynthXilinxPass : public Pass {
 		log("\n");
 		log("This command runs synthesis for Xilinx FPGAs. This command does not operate on\n");
 		log("partly selected designs. At the moment this command creates netlists that are\n");
-		log("compatible with 7-series and 6-series Xilinx devices.\n");
+		log("compatible with 7-Series Xilinx devices.\n");
 		log("\n");
 		log("    -top <module>\n");
 		log("        use the specified module as top module (default='top')\n");