From: Yunsup Lee <yunsup@cs.berkeley.edu>
Date: Sat, 22 Nov 2014 18:29:30 +0000 (-0800)
Subject: relax rv32si timer test a bit
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bebcfb0747bb31b0e2f4834f61afcf089135d3cc;p=riscv-tests.git

relax rv32si timer test a bit
---

diff --git a/isa/rv32si/timer.S b/isa/rv32si/timer.S
index d46c2fd..4048875 100644
--- a/isa/rv32si/timer.S
+++ b/isa/rv32si/timer.S
@@ -23,7 +23,7 @@ RVTEST_CODE_BEGIN
   csrsi status, 4 # enable interrupts
 
   li TESTNUM, 2
-  li a0,1000
+  li a0,10000
 loop:
   div x0, x0, x0
   addi a0, a0, -1
@@ -33,6 +33,7 @@ loop:
   TEST_PASSFAIL
 
 evec:
+  li TESTNUM, 3
   li t1, 0x80000000|IRQ_TIMER
   csrr t0, cause
   bne t0, t1, fail