From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 2 Jul 2020 13:13:48 +0000 (+0100)
Subject: use single-arg pspec for TestIssuer and Core
X-Git-Tag: div_pipeline~176
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=becaa04fcfa10fb47a276da567786a1bc8224d85;p=soc.git

use single-arg pspec for TestIssuer and Core
---

diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py
index cd779c88..aac034d7 100644
--- a/src/soc/experiment/l0_cache.py
+++ b/src/soc/experiment/l0_cache.py
@@ -264,12 +264,9 @@ class L0CacheBuffer(Elaboratable):
 
 
 class TstL0CacheBuffer(Elaboratable):
-    def __init__(self, n_units=3, regwid=16, addrwid=4, ifacetype='testpi'):
-        pspec = TestMemPspec(ldst_ifacetype=ifacetype,
-                             imem_ifacetype='',
-                             addr_wid=addrwid<<1,
-                             mask_wid=8,
-                             reg_wid=regwid)
+    def __init__(self, pspec, n_units=3):
+        regwid = pspec.reg_wid
+        addrwid = pspec.addr_wid
         self.cmpi = ConfigMemoryPortInterface(pspec)
         self.pimem = self.cmpi.pi
         self.l0 = L0CacheBuffer(n_units, self.pimem, regwid, addrwid<<1)
diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 339c6dc0..5054643c 100644
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -31,6 +31,7 @@ from soc.decoder.power_decoder import create_pdecode
 from soc.decoder.power_decoder2 import PowerDecode2
 from soc.decoder.decode2execute1 import Data
 from soc.experiment.l0_cache import TstL0CacheBuffer # test only
+from soc.config.test.test_loadstore import TestMemPspec
 import operator
 
 
@@ -53,10 +54,10 @@ def sort_fuspecs(fuspecs):
 
 
 class NonProductionCore(Elaboratable):
-    def __init__(self, addrwid=6, idepth=16, ifacetype='testpi'):
+    def __init__(self, pspec):
+        addrwid = pspec.addr_wid
         # single LD/ST funnel for memory access
-        self.l0 = TstL0CacheBuffer(n_units=1, regwid=64,
-                                   addrwid=addrwid, ifacetype=ifacetype)
+        self.l0 = TstL0CacheBuffer(pspec, n_units=1)
         pi = self.l0.l0.dports[0]
 
         # function units (only one each)
@@ -311,7 +312,12 @@ class NonProductionCore(Elaboratable):
 
 
 if __name__ == '__main__':
-    dut = NonProductionCore()
+    pspec = TestMemPspec(ldst_ifacetype='testpi',
+                         imem_ifacetype='',
+                         addr_wid=48,
+                         mask_wid=8,
+                         reg_wid=64)
+    dut = NonProductionCore(pspec)
     vl = rtlil.convert(dut, ports=dut.ports())
     with open("test_core.il", "w") as f:
         f.write(vl)
diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 2c7ea667..9ee19a4b 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -31,16 +31,10 @@ class TestIssuer(Elaboratable):
 
     efficiency and speed is not the main goal here: functional correctness is.
     """
-    def __init__(self, addrwid=6, idepth=6, ifacetype='testpi',
-                                            imemtype='testmem'):
+    def __init__(self, pspec):
         # main instruction core
-        self.core = core = NonProductionCore(addrwid, ifacetype=ifacetype)
+        self.core = core = NonProductionCore(pspec)
 
-        pspec = TestMemPspec(ldst_ifacetype=ifacetype,
-                             imem_ifacetype=imemtype,
-                             addr_wid=addrwid<<1,
-                             mask_wid=8,
-                             reg_wid=64) # instruction memory width
         # Test Instruction memory
         self.imem = ConfigFetchUnit(pspec).fu
         # one-row cache of instruction read
@@ -167,7 +161,12 @@ class TestIssuer(Elaboratable):
 
 
 if __name__ == '__main__':
-    dut = TestIssuer()
+    pspec = TestMemPspec(ldst_ifacetype='testpi',
+                         imem_ifacetype='testmem',
+                         addr_wid=48,
+                         mask_wid=8,
+                         reg_wid=64)
+    dut = TestIssuer(pspec)
     vl = rtlil.convert(dut, ports=dut.ports(), name="test_issuer")
     with open("test_issuer.il", "w") as f:
         f.write(vl)
diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py
index 14a23a8c..028872ac 100644
--- a/src/soc/simple/test/test_issuer.py
+++ b/src/soc/simple/test/test_issuer.py
@@ -17,6 +17,7 @@ from soc.decoder.power_enums import Function, XER_bits
 from soc.simple.issuer import TestIssuer
 from soc.experiment.compalu_multi import find_ok # hack
 
+from soc.config.test.test_loadstore import TestMemPspec
 from soc.simple.test.test_core import (setup_regs, check_regs,
                                        wait_for_busy_clear,
                                        wait_for_busy_hi)
@@ -66,8 +67,12 @@ class TestRunner(FHDLTestCase):
         go_insn_i = Signal()
         pc_i = Signal(32)
 
-        m.submodules.issuer = issuer = TestIssuer(ifacetype="test_bare_wb",
-                                                  imemtype="test_bare_wb")
+        pspec = TestMemPspec(ldst_ifacetype='test_bare_wb',
+                             imem_ifacetype='test_bare_wb',
+                             addr_wid=48,
+                             mask_wid=8,
+                             reg_wid=64)
+        m.submodules.issuer = issuer = TestIssuer(pspec)
         imem = issuer.imem._get_memory()
         core = issuer.core
         pdecode2 = core.pdecode2