From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 12 Feb 2015 22:28:41 +0000 (+0100)
Subject: mibuild: return verilog namespace with build
X-Git-Tag: 24jan2021_ls180~2099^2~251
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=beef7425ceacf556db164b6838dcdbe3b46ab11a;p=litex.git

mibuild: return verilog namespace with build
---

diff --git a/mibuild/altera_quartus.py b/mibuild/altera_quartus.py
index 4abccd0d..6939eb67 100644
--- a/mibuild/altera_quartus.py
+++ b/mibuild/altera_quartus.py
@@ -80,7 +80,8 @@ class AlteraQuartusPlatform(GenericPlatform):
 			fragment = fragment.get_fragment()
 		self.finalize(fragment)
 
-		v_src, named_sc, named_pc = self.get_verilog(fragment)
+		v_src, vns = self.get_verilog(fragment)
+		named_sc, named_pc = self._resolve_signals(vns)
 		v_file = build_name + ".v"
 		tools.write_to_file(v_file, v_src)
 		sources = self.sources + [(v_file, "verilog")]
@@ -90,6 +91,8 @@ class AlteraQuartusPlatform(GenericPlatform):
 
 		os.chdir("..")
 
+		return vns
+
 	def add_period_constraint(self, clk, period):
 		self.add_platform_command("""set_global_assignment -name DUTY_CYCLE 50 -section_id {clk}""", clk=clk)
 		self.add_platform_command("""set_global_assignment -name FMAX_REQUIREMENT "{freq} MHz" -section_id {clk}\n""".format(freq=str(float(1/period)*1000), clk="{clk}"), clk=clk)
diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py
index 0795fa20..6bdcbebc 100644
--- a/mibuild/generic_platform.py
+++ b/mibuild/generic_platform.py
@@ -257,8 +257,7 @@ class GenericPlatform:
 			fragment = fragment.get_fragment()
 		# generate source
 		src, vns = gen_fn(fragment)
-		named_sc, named_pc = self._resolve_signals(vns)
-		return src, named_sc, named_pc
+		return src, vns
 
 	def get_verilog(self, fragment, **kwargs):
 		return self._get_source(fragment, lambda f: verilog.convert(f, self.constraint_manager.get_io_signals(),
diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py
index 0eca9a16..d681fbe5 100644
--- a/mibuild/xilinx_ise.py
+++ b/mibuild/xilinx_ise.py
@@ -140,8 +140,11 @@ class XilinxISEPlatform(xilinx_common.XilinxGenericPlatform):
 
 		ngdbuild_opt = self.ngdbuild_opt
 
+		vns = None
+
 		if mode == "xst" or mode == "yosys":
-			v_src, named_sc, named_pc = self.get_verilog(fragment)
+			v_src, vns = self.get_verilog(fragment)
+			named_sc, named_pc = self._resolve_signals(vns)
 			v_file = build_name + ".v"
 			tools.write_to_file(v_file, v_src)
 			sources = self.sources + [(v_file, "verilog")]
@@ -158,7 +161,8 @@ class XilinxISEPlatform(xilinx_common.XilinxGenericPlatform):
 			synthesize(fragment, self.constraint_manager.get_io_signals())
 
 		if mode == "edif" or mode == "mist":
-			e_src, named_sc, named_pc = self.get_edif(fragment)
+			e_src, vns = self.get_edif(fragment)
+			named_sc, named_pc = self._resolve_signals(vns)
 			e_file = build_name + ".edif"
 			tools.write_to_file(e_file, e_src)
 			isemode = "edif"
@@ -171,6 +175,8 @@ class XilinxISEPlatform(xilinx_common.XilinxGenericPlatform):
 
 		os.chdir("..")
 
+		return vns
+
 	def add_period_constraint(self, clk, period):
 		self.add_platform_command("""NET "{clk}" TNM_NET = "GRP{clk}";
 TIMESPEC "TS{clk}" = PERIOD "GRP{clk}" """+str(period)+""" ns HIGH 50%;""", clk=clk)
diff --git a/mibuild/xilinx_vivado.py b/mibuild/xilinx_vivado.py
index 5699deba..afeb6817 100644
--- a/mibuild/xilinx_vivado.py
+++ b/mibuild/xilinx_vivado.py
@@ -102,7 +102,8 @@ class XilinxVivadoPlatform(xilinx_common.XilinxGenericPlatform):
 		if not isinstance(fragment, _Fragment):
 			fragment = fragment.get_fragment()
 		self.finalize(fragment)
-		v_src, named_sc, named_pc = self.get_verilog(fragment)
+		v_src, vns = self.get_verilog(fragment)
+		named_sc, named_pc = self._resolve_signals(vns)
 		v_file = build_name + ".v"
 		tools.write_to_file(v_file, v_src)
 		sources = self.sources + [(v_file, "verilog")]
@@ -114,6 +115,8 @@ class XilinxVivadoPlatform(xilinx_common.XilinxGenericPlatform):
 
 		os.chdir("..")
 
+		return vns
+
 	def add_period_constraint(self, clk, period):
 		self.add_platform_command("""create_clock -name {clk} -period """ +\
 			str(period) + """ [get_ports {clk}]""", clk=clk)