From: Giacomo Travaglini Date: Thu, 9 Jul 2020 09:24:16 +0000 (+0100) Subject: arch-arm: Reduce boilerplate when extracting SelfDebug from tc X-Git-Tag: v20.1.0.0~328 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bef04bca28a0847e343538da13181d80044ef23f;p=gem5.git arch-arm: Reduce boilerplate when extracting SelfDebug from tc Change-Id: I1746400617be64ac9c2f3194442734e178342909 Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31354 Tested-by: kokoro --- diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc index 300c82c2f..07d4ea894 100644 --- a/src/arch/arm/faults.cc +++ b/src/arch/arm/faults.cc @@ -723,8 +723,7 @@ ArmFault::invoke64(ThreadContext *tc, const StaticInstPtr &inst) bool ArmFault::vectorCatch(ThreadContext *tc, const StaticInstPtr &inst) { - auto *isa = static_cast(tc->getIsaPtr()); - SelfDebug * sd = isa->getSelfDebug(); + SelfDebug *sd = ArmISA::ISA::getSelfDebug(tc); VectorCatch* vc = sd->getVectorCatch(tc); if (!vc->isVCMatch()) { Fault fault = sd->testVectorCatch(tc, 0x0, this); diff --git a/src/arch/arm/insts/pseudo.cc b/src/arch/arm/insts/pseudo.cc index 3fe2dfa11..bf1fecc37 100644 --- a/src/arch/arm/insts/pseudo.cc +++ b/src/arch/arm/insts/pseudo.cc @@ -201,8 +201,11 @@ DebugStep::execute(ExecContext *xc, Trace::InstRecord *traceData) const PCState pc_state(xc->pcState()); pc_state.debugStep(false); xc->pcState(pc_state); - auto *isa = static_cast(xc->tcBase()->getIsaPtr()); - bool ldx = isa->getSelfDebug()->getSstep()->getLdx(); + + SelfDebug *sd = ArmISA::ISA::getSelfDebug(xc->tcBase()); + + bool ldx = sd->getSstep()->getLdx(); + return std::make_shared(machInst, ldx, pc_state.stepped()); diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc index 12586c756..228149115 100644 --- a/src/arch/arm/insts/static_inst.cc +++ b/src/arch/arm/insts/static_inst.cc @@ -1192,8 +1192,8 @@ ArmStaticInst::getPSTATEFromPSR(ThreadContext *tc, CPSR cpsr, CPSR spsr) const new_cpsr.daif = spsr.daif; } - auto *isa = static_cast(tc->getIsaPtr()); - SoftwareStep * ss = (isa->getSelfDebug())->getSstep(); + SelfDebug *sd = ArmISA::ISA::getSelfDebug(tc); + SoftwareStep *ss = sd->getSstep(); new_cpsr.ss = ss->debugExceptionReturnSS(tc, spsr, dest, new_cpsr.width); return new_cpsr; diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh index 2677a105c..e101d93fa 100644 --- a/src/arch/arm/insts/static_inst.hh +++ b/src/arch/arm/insts/static_inst.hh @@ -203,8 +203,7 @@ class ArmStaticInst : public StaticInst static void activateBreakpoint(ThreadContext *tc) { - auto *isa = static_cast(tc->getIsaPtr()); - SelfDebug * sd = isa->getSelfDebug(); + SelfDebug *sd = ArmISA::ISA::getSelfDebug(tc); sd->activateDebug(); } diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 3b90de134..1713da076 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -466,10 +466,19 @@ namespace ArmISA void initID64(const ArmISAParams *p); public: - SelfDebug * getSelfDebug() + SelfDebug* + getSelfDebug() const { return selfDebug; } + + static SelfDebug* + getSelfDebug(ThreadContext *tc) + { + auto *arm_isa = static_cast(tc->getIsaPtr()); + return arm_isa->getSelfDebug(); + } + RegVal readMiscRegNoEffect(int misc_reg) const; RegVal readMiscReg(int misc_reg); void setMiscRegNoEffect(int misc_reg, RegVal val); diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa index 37abb6456..d7e27a481 100644 --- a/src/arch/arm/isa/insts/ldr.isa +++ b/src/arch/arm/isa/insts/ldr.isa @@ -211,9 +211,8 @@ let {{ if self.flavor in ('exclusive', 'acex'): accCode += ''' - auto *isa = static_cast(xc->tcBase()->getIsaPtr()); - SelfDebug * sd = isa->getSelfDebug(); - sd->getSstep()->setLdx(); + SelfDebug *sd = ArmISA::ISA::getSelfDebug(xc->tcBase()); + sd->getSstep()->setLdx(); ''' self.codeBlobs["memacc_code"] = accCode @@ -293,9 +292,8 @@ let {{ ''' if self.flavor in ('exclusive', 'acex'): accCode += ''' - auto *isa = static_cast(xc->tcBase()->getIsaPtr()); - SelfDebug * sd = isa->getSelfDebug(); - sd->getSstep()->setLdx(); + SelfDebug *sd = ArmISA::ISA::getSelfDebug(xc->tcBase()); + sd->getSstep()->setLdx(); ''' self.codeBlobs["memacc_code"] = accCode diff --git a/src/arch/arm/isa/insts/ldr64.isa b/src/arch/arm/isa/insts/ldr64.isa index c9db19017..2cbc8b640 100644 --- a/src/arch/arm/isa/insts/ldr64.isa +++ b/src/arch/arm/isa/insts/ldr64.isa @@ -243,9 +243,8 @@ let {{ accCode = accCode % buildMemSuffix(self.sign, self.size) if self.flavor in ('exclusive', 'acex'): accCode += ''' - auto *isa = static_cast(xc->tcBase()->getIsaPtr()); - SelfDebug * sd = isa->getSelfDebug(); - sd->getSstep()->setLdx(); + SelfDebug *sd = ArmISA::ISA::getSelfDebug(xc->tcBase()); + sd->getSstep()->setLdx(); ''' self.codeBlobs["memacc_code"] = accCode if accEpilogCode: @@ -344,9 +343,8 @@ let {{ ''' if self.flavor in ('exp', 'acexp'): accCode += ''' - auto *isa = static_cast(xc->tcBase()->getIsaPtr()); - SelfDebug * sd = isa->getSelfDebug(); - sd->getSstep()->setLdx(); + SelfDebug *sd = ArmISA::ISA::getSelfDebug(xc->tcBase()); + sd->getSstep()->setLdx(); ''' self.codeBlobs["memacc_code"] = accCode if accEpilogCode: diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index a6205ced3..f67475bf3 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -1234,8 +1234,7 @@ TLB::translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode, //Check for Debug Exceptions if (fault == NoFault) { - auto *isa = static_cast(tc->getIsaPtr()); - SelfDebug *sd = isa->getSelfDebug(); + SelfDebug *sd = ArmISA::ISA::getSelfDebug(tc); fault = sd->testDebug(tc, req, mode); }