From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 23 Nov 2019 18:26:55 +0000 (-0800)
Subject: Conditioning abc9 on POs not accurate due to cells
X-Git-Tag: working-ls180~881^2^2~141
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bf1167bc64eba873ceaf3e4a1988a216fb3909c3;p=yosys.git

Conditioning abc9 on POs not accurate due to cells
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 4b6ec6e11..c2ac4ef7f 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -322,19 +322,10 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
 	fprintf(f, "%s\n", abc9_script.c_str());
 	fclose(f);
 
-	bool count_output = false;
-	for (auto port_name : module->ports) {
-		RTLIL::Wire *port_wire = module->wire(port_name);
-		log_assert(port_wire);
-		if (port_wire->port_output) {
-			count_output = true;
-			break;
-		}
-	}
-
+	//bool count_output = false;
 	log_push();
 
-	if (count_output)
+	//if (count_output)
 	{
 		handle_loops(design, module);
 
@@ -736,10 +727,10 @@ clone_lut:
 
 		design->remove(mapped_mod);
 	}
-	else
-	{
-		log("Don't call ABC as there is nothing to map.\n");
-	}
+	//else
+	//{
+	//	log("Don't call ABC as there is nothing to map.\n");
+	//}
 
 	if (cleanup)
 	{