From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 11 Dec 2021 14:18:47 +0000 (+0000)
Subject: add new ConfigFetchUnit option "mmu_cache_wb" which connects up
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bf1e457649f9b1322e46030fc0e3cbfba4315134;p=soc.git

add new ConfigFetchUnit option "mmu_cache_wb" which connects up
directly to LoadstStore1 I-Cache
---

diff --git a/src/soc/config/ifetch.py b/src/soc/config/ifetch.py
index a40c2727..fd9d9d16 100644
--- a/src/soc/config/ifetch.py
+++ b/src/soc/config/ifetch.py
@@ -18,6 +18,10 @@ class ConfigFetchUnit:
                    'bare_wb': BareFetchUnit,
                    #'test_cache_wb': TestCacheFetchUnit
                   }
+        if self.pspec.imem_ifacetype in ['mmu_cache_wb', 'test_mmu_cache_wb']:
+            self.fu = self.lsmem.lsi.icache # ICache already FetchUnitInterface
+            return
+
         fukls = fudict[pspec.imem_ifacetype]
         self.fu = fukls(pspec)