From: Cesar Strauss <cestrauss@gmail.com>
Date: Sun, 7 Mar 2021 09:41:47 +0000 (-0300)
Subject: Implement the VL==0 loop
X-Git-Tag: convert-csv-opcode-to-binary~98
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bf1ee9d6aa9790eb88c67c162591c5b7de19e8e7;p=soc.git

Implement the VL==0 loop

Just after decode, decide whether we proceed to Execute, or shortcut it
directly to the next Fetch.
---

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index f16eb8b5..f6501990 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -304,10 +304,19 @@ class TestIssuerInternal(Elaboratable):
                     sync += core.state.eq(cur_state)
                     sync += core.raw_insn_i.eq(dec_opcode_i)
                     sync += core.bigendian_i.eq(self.core_bigendian_i)
-                    # TODO: loop into INSN_FETCH if it's a vector instruction
-                    #       and VL == 0.  this because VL==0 is a for-loop
-                    #       from 0 to 0 i.e. always, always a NOP.
-                    m.next = "INSN_EXECUTE"  # move to "execute"
+                    # loop into INSN_FETCH if it's a vector instruction
+                    # and VL == 0.  this because VL==0 is a for-loop
+                    # from 0 to 0 i.e. always, always a NOP.
+                    cur_vl = cur_state.svstate.vl
+                    with m.If(~pdecode2.no_out_vec & (cur_vl == 0)):
+                        # update the PC before fetching the next instruction
+                        # since we are in a VL==0 loop, no instruction was
+                        # executed that we could be overwriting
+                        comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
+                        comb += self.state_w_pc.data_i.eq(nia)
+                        m.next = "INSN_FETCH"
+                    with m.Else():
+                        m.next = "INSN_EXECUTE"  # move to "execute"
 
             with m.State("INSN_EXECUTE"):
                 comb += exec_insn_valid_i.eq(1)