From: Luke Kenneth Casson Leighton Date: Fri, 23 Apr 2021 15:14:01 +0000 (+0100) Subject: more openpower-isa conversion X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bf24feeeeb2ae9f4af536802dc3f7f9fb84666d9;p=soc.git more openpower-isa conversion --- diff --git a/src/soc/fu/mmu/test/test_non_production_core.py b/src/soc/fu/mmu/test/test_non_production_core.py index ee01ca5b..c498d71b 100644 --- a/src/soc/fu/mmu/test/test_non_production_core.py +++ b/src/soc/fu/mmu/test/test_non_production_core.py @@ -12,7 +12,7 @@ from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program from openpower.decoder.isa.all import ISA from soc.config.endian import bigendian -from soc.consts import MSR +from openpower.consts import MSR from soc.fu.test.common import ( diff --git a/src/soc/fu/mmu/test/test_pipe_caller.py b/src/soc/fu/mmu/test/test_pipe_caller.py index df489dbc..24d39044 100644 --- a/src/soc/fu/mmu/test/test_pipe_caller.py +++ b/src/soc/fu/mmu/test/test_pipe_caller.py @@ -14,7 +14,7 @@ from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program from openpower.decoder.isa.all import ISA from soc.config.endian import bigendian -from soc.consts import MSR +from openpower.consts import MSR from soc.fu.test.common import ( diff --git a/src/soc/fu/shift_rot/formal/proof_main_stage.py b/src/soc/fu/shift_rot/formal/proof_main_stage.py index dde891ec..5d8bae28 100644 --- a/src/soc/fu/shift_rot/formal/proof_main_stage.py +++ b/src/soc/fu/shift_rot/formal/proof_main_stage.py @@ -16,7 +16,7 @@ from soc.fu.shift_rot.rotator import right_mask, left_mask from soc.fu.shift_rot.pipe_data import ShiftRotPipeSpec from soc.fu.shift_rot.sr_input_record import CompSROpSubset from openpower.decoder.power_enums import MicrOp -from soc.consts import field +from openpower.consts import field import unittest from nmutil.extend import exts diff --git a/src/soc/fu/spr/test/test_pipe_caller.py b/src/soc/fu/spr/test/test_pipe_caller.py index 87ba83ca..1f70041c 100644 --- a/src/soc/fu/spr/test/test_pipe_caller.py +++ b/src/soc/fu/spr/test/test_pipe_caller.py @@ -14,7 +14,7 @@ from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program from openpower.decoder.isa.all import ISA from soc.config.endian import bigendian -from soc.consts import MSR +from openpower.consts import MSR from soc.fu.test.common import ( diff --git a/src/soc/fu/trap/formal/proof_main_stage.py b/src/soc/fu/trap/formal/proof_main_stage.py index c88c0ac2..235df615 100644 --- a/src/soc/fu/trap/formal/proof_main_stage.py +++ b/src/soc/fu/trap/formal/proof_main_stage.py @@ -19,7 +19,7 @@ from nmigen.cli import rtlil from nmutil.extend import exts from nmutil.formaltest import FHDLTestCase -from soc.consts import MSR, MSRb, PI, TT, field +from openpower.consts import MSR, MSRb, PI, TT, field from openpower.decoder.power_enums import MicrOp diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py index 5b272e63..afc2e677 100644 --- a/src/soc/fu/trap/main_stage.py +++ b/src/soc/fu/trap/main_stage.py @@ -20,7 +20,7 @@ from soc.experiment.mem_types import LDSTException from openpower.decoder.power_fields import DecodeFields from openpower.decoder.power_fieldsn import SignalBitRange -from soc.consts import MSR, PI, TT, field, field_slice +from openpower.consts import MSR, PI, TT, field, field_slice def msr_copy(msr_o, msr_i, zero_me=True): diff --git a/src/soc/fu/trap/test/test_pipe_caller.py b/src/soc/fu/trap/test/test_pipe_caller.py index f9fa09ce..b9cea5c5 100644 --- a/src/soc/fu/trap/test/test_pipe_caller.py +++ b/src/soc/fu/trap/test/test_pipe_caller.py @@ -15,7 +15,7 @@ from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program from openpower.decoder.isa.all import ISA from soc.config.endian import bigendian -from soc.consts import MSR +from openpower.consts import MSR from soc.fu.test.common import (TestAccumulatorBase, TestCase, ALUHelpers) from soc.fu.trap.pipeline import TrapBasePipe diff --git a/src/soc/fu/trap/trap_input_record.py b/src/soc/fu/trap/trap_input_record.py index 0d08f5ec..5b86693f 100644 --- a/src/soc/fu/trap/trap_input_record.py +++ b/src/soc/fu/trap/trap_input_record.py @@ -1,6 +1,6 @@ from soc.fu.base_input_record import CompOpSubsetBase from openpower.decoder.power_enums import (MicrOp, Function) -from soc.consts import TT +from openpower.consts import TT from soc.experiment.mem_types import LDSTException class CompTrapOpSubset(CompOpSubsetBase): diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index 4afa0d7a..6c2e3cf6 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -27,24 +27,24 @@ from openpower.decoder.power_decoder import create_pdecode from openpower.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder from openpower.decoder.decode2execute1 import IssuerDecode2ToOperand from openpower.decoder.decode2execute1 import Data +from openpower.decoder.power_enums import (MicrOp, SVP64PredInt, SVP64PredCR, + SVP64PredMode) +from openpower.state import CoreState +from openpower.consts import (CR, SVP64CROffs) from soc.experiment.testmem import TestMemory # test only for instructions from soc.regfile.regfiles import StateRegs, FastRegs from soc.simple.core import NonProductionCore from soc.config.test.test_loadstore import TestMemPspec from soc.config.ifetch import ConfigFetchUnit -from openpower.decoder.power_enums import (MicrOp, SVP64PredInt, SVP64PredCR, - SVP64PredMode) -from soc.consts import (CR, SVP64CROffs) from soc.debug.dmi import CoreDebug, DMIInterface from soc.debug.jtag import JTAG from soc.config.pinouts import get_pinspecs -from soc.config.state import CoreState from soc.interrupts.xics import XICS_ICP, XICS_ICS from soc.bus.simple_gpio import SimpleGPIO from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W from soc.clock.select import ClockSelect from soc.clock.dummypll import DummyPLL -from soc.sv.svstate import SVSTATERec +from openpower.sv.svstate import SVSTATERec from nmutil.util import rising_edge