From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Fri, 26 Jul 2013 13:42:44 +0000 (+0200)
Subject: Use RenameClockDomains decorator instead of add_submodule
X-Git-Tag: 24jan2021_ls180~2854
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bf325594eec9fa726e273f3f8db0800f4bcba1b8;p=litex.git

Use RenameClockDomains decorator instead of add_submodule
---

diff --git a/milkymist/dvisampler/analysis.py b/milkymist/dvisampler/analysis.py
index bf1663f5..c7d24786 100644
--- a/milkymist/dvisampler/analysis.py
+++ b/milkymist/dvisampler/analysis.py
@@ -137,8 +137,9 @@ class FrameExtraction(Module, AutoCSR):
 			vsync_r.eq(self.vsync)
 		]
 
-		fifo = AsyncFIFO(layout_len(frame_layout), 512)
-		self.add_submodule(fifo, {"write": "pix", "read": "sys"})
+		fifo = RenameClockDomains(AsyncFIFO(layout_len(frame_layout), 512),
+			{"write": "pix", "read": "sys"})
+		self.submodules += fifo
 		self.comb += [
 			fifo.we.eq(fifo_stb),
 			fifo.din.eq(fifo_in.raw_bits()),
diff --git a/milkymist/dvisampler/chansync.py b/milkymist/dvisampler/chansync.py
index ce6bbaca..272408e1 100644
--- a/milkymist/dvisampler/chansync.py
+++ b/milkymist/dvisampler/chansync.py
@@ -56,8 +56,8 @@ class ChanSync(Module, AutoCSR):
 
 			###
 		
-			syncbuffer = _SyncBuffer(layout_len(channel_layout), depth)
-			self.add_submodule(syncbuffer, "pix")
+			syncbuffer = RenameClockDomains(_SyncBuffer(layout_len(channel_layout), depth), "pix")
+			self.submodules += syncbuffer
 			self.comb += [
 				syncbuffer.din.eq(data_in.raw_bits()),
 				data_out.raw_bits().eq(syncbuffer.dout)
diff --git a/milkymist/dvisampler/debug.py b/milkymist/dvisampler/debug.py
index 52df4e6d..39326640 100644
--- a/milkymist/dvisampler/debug.py
+++ b/milkymist/dvisampler/debug.py
@@ -25,8 +25,9 @@ class RawDVISampler(Module, AutoCSR):
 			self.data0_cap.serdesstrobe.eq(self.clocking.serdesstrobe)
 		]
 
-		fifo = AsyncFIFO(10, 256)
-		self.add_submodule(fifo, {"write": "pix", "read": "sys"})
+		fifo = RenameClockDomains(AsyncFIFO(10, 256),
+			{"write": "pix", "read": "sys"})
+		self.submodules += fifo
 		self.comb += [
 			fifo.din.eq(self.data0_cap.d),
 			fifo.we.eq(1)
diff --git a/milkymist/framebuffer/lib.py b/milkymist/framebuffer/lib.py
index 18b0be40..81bfa44b 100644
--- a/milkymist/framebuffer/lib.py
+++ b/milkymist/framebuffer/lib.py
@@ -128,8 +128,9 @@ class FIFO(Module):
 		###
 
 		data_width = 2+2*3*bpc_dac
-		fifo = AsyncFIFO(data_width, 512)
-		self.add_submodule(fifo, {"write": "sys", "read": "vga"})
+		fifo = RenameClockDomains(AsyncFIFO(data_width, 512),
+			{"write": "sys", "read": "vga"})
+		self.submodules += fifo
 		fifo_in = self.dac.payload
 		fifo_out = Record(dac_layout)
 		self.comb += [
diff --git a/tb/dvisampler/chansync.py b/tb/dvisampler/chansync.py
index cc38e07e..9a8fbf77 100644
--- a/tb/dvisampler/chansync.py
+++ b/tb/dvisampler/chansync.py
@@ -7,8 +7,7 @@ class TB(Module):
 	def __init__(self, test_seq_it):
 		self.test_seq_it = test_seq_it
 
-		self.chansync = ChanSync()
-		self.add_submodule(self.chansync, {"pix": "sys"})
+		self.submodules.chansync = RenameClockDomains(ChanSync(), {"pix": "sys"})
 		self.comb += self.chansync.valid_i.eq(1)
 
 	def do_simulation(self, s):