From: Maciej W. Rozycki <macro@imgtec.com>
Date: Thu, 8 Dec 2016 22:53:39 +0000 (+0000)
Subject: ARM/GAS: Correct an `index' global shadowing error
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bf355b690f07315bf2704e349c4f1c9ca611f031;p=binutils-gdb.git

ARM/GAS: Correct an `index' global shadowing error

Fix a commit 008a97eff0ca ("[GAS][ARM]Generate unpredictable warning for
pc used in data processing instructions with register-shifted register
operand.") build regression:

cc1: warnings being treated as errors
.../gas/config/tc-arm.c: In function 'encode_arm_shift':
.../gas/config/tc-arm.c:7439: error: declaration of 'index' shadows a global declaration
/usr/include/string.h:303: error: shadowed declaration is here
make[4]: *** [tc-arm.o] Error 1

in a way following commit 91d6fa6a035c ("Add -Wshadow to the gcc command
line options used when compiling the binutils.").

	gas/
	* config/tc-arm.c (encode_arm_shift): Rename `index' local
	variable to `op_index'.
---

diff --git a/gas/ChangeLog b/gas/ChangeLog
index e2e340c16bf..7def377fc5a 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
+
+	* config/tc-arm.c (encode_arm_shift): Rename `index' local
+	variable to `op_index'.
+
 2016-12-08  Alan Modra  <amodra@gmail.com>
 
 	* configure: Regenerate.
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 41ab13e5d17..c15f3db3df6 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -7436,14 +7436,14 @@ encode_arm_shift (int i)
   /* register-shifted register.  */
   if (inst.operands[i].immisreg)
     {
-      int index;
-      for (index = 0; index <= i; ++index)
+      int op_index;
+      for (op_index = 0; op_index <= i; ++op_index)
 	{
 	  /* Check the operand only when it's presented.  In pre-UAL syntax,
 	     if the destination register is the same as the first operand, two
 	     register form of the instruction can be used.  */
-	  if (inst.operands[index].present && inst.operands[index].isreg
-	      && inst.operands[index].reg == REG_PC)
+	  if (inst.operands[op_index].present && inst.operands[op_index].isreg
+	      && inst.operands[op_index].reg == REG_PC)
 	    as_warn (UNPRED_REG ("r15"));
 	}