From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 27 May 2019 19:19:21 +0000 (-0700)
Subject: Remove mapped_mod when done
X-Git-Tag: working-ls180~1208^2~267
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bf3b8d5e45771a543c2481dee5b1b3a9aba0881e;p=yosys.git

Remove mapped_mod when done
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 475508e02..acbab959e 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -937,6 +937,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 		//log("ABC RESULTS:        internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
 		log("ABC RESULTS:           input signals: %8d\n", in_wires);
 		log("ABC RESULTS:          output signals: %8d\n", out_wires);
+
+		design->remove(mapped_mod);
 	}
 	//else
 	//{