From: whitequark <whitequark@whitequark.org>
Date: Thu, 6 Feb 2020 19:38:21 +0000 (+0000)
Subject: xilinx_{7series,ultrascale}: run `report_methodology`.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bf5e4e20d936d085d5490ab6285ca0dcdaa528a3;p=nmigen.git

xilinx_{7series,ultrascale}: run `report_methodology`.

This can expose important timing issues, such as #301.
---

diff --git a/nmigen/vendor/xilinx_7series.py b/nmigen/vendor/xilinx_7series.py
index 899defc..50f6636 100644
--- a/nmigen/vendor/xilinx_7series.py
+++ b/nmigen/vendor/xilinx_7series.py
@@ -38,6 +38,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
         * ``{{name}}_clock_utilization.rpt``:  Vivado report.
         * ``{{name}}_route_status.rpt``: Vivado report.
         * ``{{name}}_drc.rpt``: Vivado report.
+        * ``{{name}}_methodology.rpt``: Vivado report.
         * ``{{name}}_timing.rpt``: Vivado report.
         * ``{{name}}_power.rpt``: Vivado report.
         * ``{{name}}_route.dcp``: Vivado design checkpoint.
@@ -116,6 +117,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
             write_checkpoint -force {{name}}_route.dcp
             report_route_status -file {{name}}_route_status.rpt
             report_drc -file {{name}}_drc.rpt
+            report_methodology -file {{name}}_methodology.rpt
             report_timing_summary -datasheet -max_paths 10 -file {{name}}_timing.rpt
             report_power -file {{name}}_power.rpt
             {{get_override("script_before_bitstream")|default("# (script_before_bitstream placeholder)")}}
diff --git a/nmigen/vendor/xilinx_ultrascale.py b/nmigen/vendor/xilinx_ultrascale.py
index 15aadd4..74d5986 100644
--- a/nmigen/vendor/xilinx_ultrascale.py
+++ b/nmigen/vendor/xilinx_ultrascale.py
@@ -38,6 +38,7 @@ class XilinxUltraScalePlatform(TemplatedPlatform):
         * ``{{name}}_clock_utilization.rpt``:  Vivado report.
         * ``{{name}}_route_status.rpt``: Vivado report.
         * ``{{name}}_drc.rpt``: Vivado report.
+        * ``{{name}}_methodology.rpt``: Vivado report.
         * ``{{name}}_timing.rpt``: Vivado report.
         * ``{{name}}_power.rpt``: Vivado report.
         * ``{{name}}_route.dcp``: Vivado design checkpoint.
@@ -116,6 +117,7 @@ class XilinxUltraScalePlatform(TemplatedPlatform):
             write_checkpoint -force {{name}}_route.dcp
             report_route_status -file {{name}}_route_status.rpt
             report_drc -file {{name}}_drc.rpt
+            report_methodology -file {{name}}_methodology.rpt
             report_timing_summary -datasheet -max_paths 10 -file {{name}}_timing.rpt
             report_power -file {{name}}_power.rpt
             {{get_override("script_before_bitstream")|default("# (script_before_bitstream placeholder)")}}