From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 28 Oct 2022 12:20:10 +0000 (+0100)
Subject: fix dsld pseudocode to use ROTL64 instead of ROTL128
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bf667e4355452cbf69bd0eb7bbc6e692f64e7af4;p=openpower-isa.git

fix dsld pseudocode to use ROTL64 instead of ROTL128
---

diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn
index e9e4beab..0de85f27 100644
--- a/openpower/isa/svfixedarith.mdwn
+++ b/openpower/isa/svfixedarith.mdwn
@@ -56,10 +56,10 @@ VA2-Form
 Pseudo-code:
 
     n <- (RB)[58:63]
-    v <- ROTL128([0]*64 || (RA), n)
-    mask <- ¬MASK(64, 63-n)
-    RT <- v[64:127] | ((RC) & mask)
-    RS <- v[0:63]
+    v <- ROTL64((RA), n)
+    mask <- MASK(64, 63-n)
+    RT <- (v[0:63] & mask) | ((RC) & ¬mask)
+    RS <- v[0:63] & ¬mask
 
 Special Registers Altered:
 
diff --git a/src/openpower/test/bigint/bigint_cases.py b/src/openpower/test/bigint/bigint_cases.py
index 665f30b0..9abdce55 100644
--- a/src/openpower/test/bigint/bigint_cases.py
+++ b/src/openpower/test/bigint/bigint_cases.py
@@ -173,7 +173,6 @@ class SVP64BigIntCases(TestAccumulatorBase):
         svstate.vl = 3
         svstate.maxvl = 3
         e = ExpectedState(pc=8, int_regs=gprs)
-        e.intregs[5] = 0x0000_0000_0000_0000     # it's down the other end...
         self.add_case(prog, gprs, expected=e, initial_svstate=svstate)
 
     def case_sv_bigint_mul_by_scalar(self):