From: Wilco Dijkstra <wdijkstr@arm.com>
Date: Thu, 26 Nov 2015 09:46:34 +0000 (+0000)
Subject: [AArch64] Update patterns to support FP zero
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bf8e1b52f72d079d99173a6742f0070c632cc736;p=gcc.git

[AArch64] Update patterns to support FP zero

2015-11-26  Wilco Dijkstra  <wdijkstr@arm.com>

	* config/aarch64/aarch64.md (cbranch<mode>4): Use
	aarch64_fp_compare_operand.
	(store_pairsf): Use aarch64_reg_or_fp_zero.
	(store_pairdf): Likewise.
	(cstore<mode>4): Use aarch64_fp_compare_operand.
	(cmov<mode>6): Likewise.
	* config/aarch64/aarch64-ldpstp.md: Use aarch64_reg_or_fp_zero.

From-SVN: r230927
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 766f034ef60..56dd588c52e 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2015-11-26  Wilco Dijkstra  <wdijkstr@arm.com>
+
+	* config/aarch64/aarch64.md (cbranch<mode>4): Use
+	aarch64_fp_compare_operand.
+	(store_pairsf): Use aarch64_reg_or_fp_zero.
+	(store_pairdf): Likewise.
+	(cstore<mode>4): Use aarch64_fp_compare_operand.
+	(cmov<mode>6): Likewise.
+	* config/aarch64/aarch64-ldpstp.md: Use aarch64_reg_or_fp_zero.
+
 2015-11-25  Aditya Kumar  <aditya.k7@samsung.com>
 	    Sebastian Pop  <s.pop@samsung.com>
 
diff --git a/gcc/config/aarch64/aarch64-ldpstp.md b/gcc/config/aarch64/aarch64-ldpstp.md
index 458829ce51d..3f88703eabd 100644
--- a/gcc/config/aarch64/aarch64-ldpstp.md
+++ b/gcc/config/aarch64/aarch64-ldpstp.md
@@ -80,9 +80,9 @@
 
 (define_peephole2
   [(set (match_operand:GPF 0 "aarch64_mem_pair_operand" "")
-	(match_operand:GPF 1 "register_operand" ""))
+	(match_operand:GPF 1 "aarch64_reg_or_fp_zero" ""))
    (set (match_operand:GPF 2 "memory_operand" "")
-	(match_operand:GPF 3 "register_operand" ""))]
+	(match_operand:GPF 3 "aarch64_reg_or_fp_zero" ""))]
   "aarch64_operands_ok_for_ldpstp (operands, false, <MODE>mode)"
   [(parallel [(set (match_dup 0) (match_dup 1))
 	      (set (match_dup 2) (match_dup 3))])]
@@ -349,13 +349,13 @@
 (define_peephole2
   [(match_scratch:DI 8 "r")
    (set (match_operand:GPF 0 "memory_operand" "")
-	(match_operand:GPF 1 "aarch64_reg_or_zero" ""))
+	(match_operand:GPF 1 "aarch64_reg_or_fp_zero" ""))
    (set (match_operand:GPF 2 "memory_operand" "")
-	(match_operand:GPF 3 "aarch64_reg_or_zero" ""))
+	(match_operand:GPF 3 "aarch64_reg_or_fp_zero" ""))
    (set (match_operand:GPF 4 "memory_operand" "")
-	(match_operand:GPF 5 "aarch64_reg_or_zero" ""))
+	(match_operand:GPF 5 "aarch64_reg_or_fp_zero" ""))
    (set (match_operand:GPF 6 "memory_operand" "")
-	(match_operand:GPF 7 "aarch64_reg_or_zero" ""))
+	(match_operand:GPF 7 "aarch64_reg_or_fp_zero" ""))
    (match_dup 8)]
   "aarch64_operands_adjust_ok_for_ldpstp (operands, false, <MODE>mode)"
   [(const_int 0)]
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index c11e8ec01df..64a40ae3175 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -247,7 +247,7 @@
 (define_expand "cbranch<mode>4"
   [(set (pc) (if_then_else (match_operator 0 "aarch64_comparison_operator"
 			    [(match_operand:GPF 1 "register_operand" "")
-			     (match_operand:GPF 2 "aarch64_reg_or_zero" "")])
+			     (match_operand:GPF 2 "aarch64_fp_compare_operand" "")])
 			   (label_ref (match_operand 3 "" ""))
 			   (pc)))]
   ""
@@ -1382,9 +1382,9 @@
 ;; fairly lax checking on the second memory operation.
 (define_insn "store_pairsf"
   [(set (match_operand:SF 0 "aarch64_mem_pair_operand" "=Ump,Ump")
-	(match_operand:SF 1 "register_operand" "w,*r"))
+	(match_operand:SF 1 "aarch64_reg_or_fp_zero" "w,*rY"))
    (set (match_operand:SF 2 "memory_operand" "=m,m")
-	(match_operand:SF 3 "register_operand" "w,*r"))]
+	(match_operand:SF 3 "aarch64_reg_or_fp_zero" "w,*rY"))]
   "rtx_equal_p (XEXP (operands[2], 0),
 		plus_constant (Pmode,
 			       XEXP (operands[0], 0),
@@ -1398,9 +1398,9 @@
 
 (define_insn "store_pairdf"
   [(set (match_operand:DF 0 "aarch64_mem_pair_operand" "=Ump,Ump")
-	(match_operand:DF 1 "register_operand" "w,*r"))
+	(match_operand:DF 1 "aarch64_reg_or_fp_zero" "w,*rY"))
    (set (match_operand:DF 2 "memory_operand" "=m,m")
-	(match_operand:DF 3 "register_operand" "w,*r"))]
+	(match_operand:DF 3 "aarch64_reg_or_fp_zero" "w,*rY"))]
   "rtx_equal_p (XEXP (operands[2], 0),
 		plus_constant (Pmode,
 			       XEXP (operands[0], 0),
@@ -2947,7 +2947,7 @@
   [(set (match_operand:SI 0 "register_operand" "")
 	(match_operator:SI 1 "aarch64_comparison_operator"
 	 [(match_operand:GPF 2 "register_operand" "")
-	  (match_operand:GPF 3 "register_operand" "")]))]
+	  (match_operand:GPF 3 "aarch64_fp_compare_operand" "")]))]
   ""
   "
   operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2],
@@ -3051,7 +3051,7 @@
 	(if_then_else:GPF
 	 (match_operator 1 "aarch64_comparison_operator"
 	  [(match_operand:GPF 2 "register_operand" "")
-	   (match_operand:GPF 3 "register_operand" "")])
+	   (match_operand:GPF 3 "aarch64_fp_compare_operand" "")])
 	 (match_operand:GPF 4 "register_operand" "")
 	 (match_operand:GPF 5 "register_operand" "")))]
   ""