From: lkcl <lkcl@web>
Date: Mon, 10 Apr 2023 21:33:47 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls012_v1~20
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bf8e855b447c8fa4d8527066c0aa47d92c606109;p=libreriscv.git

---

diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn
index 8f6e8aa27..5e62ec9c5 100644
--- a/openpower/sv/normal.mdwn
+++ b/openpower/sv/normal.mdwn
@@ -50,7 +50,7 @@ independent and may easily be parallelised to give high performance,
 regardless of the value of VL.
 
 The Mode table for Arithmetic and Logical operations,
-bring bits 19-23 of SVP64 `RM`, is laid out as
+being bits 19-23 of SVP64 `RM`, is laid out as
 follows:
 
 | 0-1 |  2  |  3   4  |  description              |