From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 10 Oct 2014 13:32:36 +0000 (+0200)
Subject: mila: simplify usage
X-Git-Tag: 24jan2021_ls180~2575^2~56
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bf95ea6c1c77e8e6f471418cf600875f264d5e5a;p=litex.git

mila: simplify usage
---

diff --git a/miscope/mila.py b/miscope/mila.py
index 9fa3637e..765ac840 100644
--- a/miscope/mila.py
+++ b/miscope/mila.py
@@ -9,40 +9,59 @@ from miscope.storage import Recorder, RunLengthEncoder
 
 from mibuild.tools import write_to_file
 
+def _getattr_all(l, attr):
+	it = iter(l)
+	r = getattr(next(it), attr)
+	for e in it:
+		if getattr(e, attr) != r:
+			raise ValueError
+	return r
+
 class MiLa(Module, AutoCSR):
-	def __init__(self, width, depth, ports, with_rle=False, clk_domain="sys"):
-		self.width = width
+	def __init__(self, depth, dat, with_rle=False, clk_domain="sys"):
 		self.depth = depth
 		self.with_rle = with_rle
-		self.ports = ports
+		self.clk_domain = clk_domain
+		self.ports = []
+		self.width = flen(dat)
+
+		self.stb = Signal(reset=1)
+		self.dat = dat
 
-		self.sink = Record(dat_layout(width))
+	def add_port(self, port_class):
+		port = port_class(self.width)
+		self.ports.append(port)
 
-		if clk_domain is not "sys":
-			fifo = AsyncFIFO([("dat", width)], 32)
-			self.submodules += RenameClockDomains(fifo, {"write": clk_domain, "read": "sys"})
+	def do_finalize(self):
+		if self.clk_domain is not "sys":
+			fifo = AsyncFIFO([("dat", self.width)], 32)
+			self.submodules += RenameClockDomains(fifo, {"write": self.clk_domain, "read": "sys"})
 			self.comb += [
-				fifo.sink.stb.eq(self.sink.stb),
-				fifo.sink.dat.eq(self.sink.dat)
+				fifo.sink.stb.eq(self.stb),
+				fifo.sink.dat.eq(self.dat)
 			]
-			sink = Record(dat_layout(width))
+			sink = Record(dat_layout(self.width))
 			self.comb += [
 				sink.stb.eq(fifo.source.stb),
 				sink.dat.eq(fifo.source.dat),
 				fifo.source.ack.eq(1)
 			]
 		else:
-			sink = self.sink
+			sink = Record(dat_layout(self.width))
+			self.comb += [
+				sink.stb.eq(self.stb),
+				sink.dat.eq(self.dat)
+			]
 
-		self.submodules.trigger = trigger = Trigger(width, ports)
-		self.submodules.recorder = recorder = Recorder(width, depth)
+		self.submodules.trigger = trigger = Trigger(self.width, self.ports)
+		self.submodules.recorder = recorder = Recorder(self.width, self.depth)
 		self.comb += [
 			sink.connect(trigger.sink),
 			trigger.source.connect(recorder.trig_sink)
 		]
 
-		if with_rle:
-			self.submodules.rle = rle = RunLengthEncoder(width)
+		if self.with_rle:
+			self.submodules.rle = rle = RunLengthEncoder(self.width)
 			self.comb += [
 				sink.connect(rle.sink),
 				rle.source.connect(recorder.dat_sink)