From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 27 Apr 2018 09:06:13 +0000 (+0100)
Subject: clean up Makefile
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bf9cc46e899ec12ae4030a61f640dbf1eb928246;p=pinmux.git

clean up Makefile
---

diff --git a/Makefile b/Makefile
index 23c3cd9..9c2c254 100644
--- a/Makefile
+++ b/Makefile
@@ -1,47 +1,24 @@
-### Makefile for the cclass project
+### Makefile for the cclass project (test)
 
-TOP_MODULE:=mkbus
-TOP_FILE:=bus.bsv
-TOP_DIR:=./m_class/bsv_src/
-WORKING_DIR := $(shell pwd)
-
-BSVINCDIR:= .:%/Prelude:%/Libraries:%/Libraries/BlueNoC:./m_class/bsv_src:./src/bsv/bsv_lib/
 default: gen_pinmux gen_verilog
 
-check-blue:
-	@if test -z "$$BLUESPECDIR"; then echo "BLUESPECDIR variable not set"; exit 1; fi; 
-
-###### Setting the variables for bluespec compile #$############################
-BSVCOMPILEOPTS:= -check-assert -suppress-warnings G0020 -keep-fires -opt-undetermined-vals -remove-false-rules -remove-empty-rules -remove-starved-rules 
-BSVLINKOPTS:=-parallel-sim-link 8 -keep-fires
-VERILOGDIR:=./verilog/
-BSVBUILDDIR:=./bsv_build/
-BSVOUTDIR:=./bin
-################################################################################
-
-########## BSIM COMPILE, LINK AND SIMULATE TARGETS #################################
-.PHONY: check-restore
-check-restore:
-	@if [ "$(define_macros)" != "$(old_define_macros)" ];	then	make clean ;	fi;
 
+########## BSIM COMPILE, LINK AND SIMULATE TARGETS ##########################
 .PHONY: gen_pinmux
 gen_pinmux: 
 	@python ./src/pinmux_generator.py -v -o test
 
 .PHONY: gen_verilog 
-gen_verilog: check-restore check-blue 
-	@echo Compiling mkTbSoc in Verilog for simulations ...
-	@mkdir -p $(BSVBUILDDIR); 
-	@mkdir -p $(VERILOGDIR); 
-	bsc -u -verilog -elab -vdir $(VERILOGDIR) -bdir $(BSVBUILDDIR) -info-dir $(BSVBUILDDIR) $(define_macros) -D verilog=True $(BSVCOMPILEOPTS) -verilog-filter ${BLUESPECDIR}/bin/basicinout -p $(BSVINCDIR) -g $(TOP_MODULE) $(TOP_DIR)/$(TOP_FILE) 2>&1 | tee bsv_compile.log
-	@echo Compilation finished
+gen_verilog:
+	make -C test gen_verilog
 
-########################################################################################
+#############################################################################
 
 .PHONY: clean
 clean:
-	rm -rf $(BSVBUILDDIR) *.log $(BSVOUTDIR) ./bbl*
-	rm -rf verilog obj_dir test/bsv_src src/*.pyc
+	make -C test clean
+	find . -name "*.pyc" | xargs rm -f
+	find . -name "__pycache__" | xargs rm -fr
 
 pep8:
 	autopep8 -a -a -a --experimental -r -i src