From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 15 Nov 2020 03:12:30 +0000 (+0000)
Subject: mention idea TODO of going into 32-bit mode for 1 instruction
X-Git-Tag: convert-csv-opcode-to-binary~1814
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bf9d2d9269944f371854c39c1f0b76fb6d83c1fd;p=libreriscv.git

mention idea TODO of going into 32-bit mode for 1 instruction
https://bugs.libre-soc.org/show_bug.cgi?id=238#c2
---

diff --git a/openpower/sv/16_bit_compressed.mdwn b/openpower/sv/16_bit_compressed.mdwn
index fa704f2ce..4dcc91208 100644
--- a/openpower/sv/16_bit_compressed.mdwn
+++ b/openpower/sv/16_bit_compressed.mdwn
@@ -55,6 +55,10 @@ also need to be dedicated to saying if 16 bit mode is to be continued.
 
 # Opcode Allocation Ideas
 
+* one bit from the 16-bit mode is used to indicate that 32-bit mode
+  is to be dropped into for only one single instruction
+  <https://bugs.libre-soc.org/show_bug.cgi?id=238#c2>
+
 ## Opcodes exploration (Attempt 1)
 
 ### Branch