From: Nathanael Premillieu <nathanael.premillieu@irisa.fr>
Date: Tue, 25 Sep 2012 16:49:40 +0000 (-0500)
Subject: ARM: Inst writing to cntrlReg registers not set as control inst
X-Git-Tag: stable_2013_06_16~391
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bfffbb67976fc4a01185e36c8eaf755454cf19a5;p=gem5.git

ARM: Inst writing to cntrlReg registers not set as control inst

Deletion of the fact that instructions that writes to registers of type
"cntrlReg" are not set as control instruction (flag IsControl not set).
---

diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 62684f5af..64deef044 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -118,7 +118,7 @@ let {{
         return ('IntReg', 'uw', idx, None, srtNormal)
 
     def cntrlReg(idx, id = srtNormal, type = 'uw'):
-        return ('ControlReg', type, idx, (None, None, 'IsControl'), id)
+        return ('ControlReg', type, idx, None, id)
 
     def cntrlRegNC(idx, id = srtNormal, type = 'uw'):
         return ('ControlReg', type, idx, None, id)