From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 25 Sep 2014 12:14:11 +0000 (+0200)
Subject: clean up (thanks to Sebastien)
X-Git-Tag: 24jan2021_ls180~2572^2~198
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c008dfdd989c25f757a2c1adeaf76f4aeb1f5798;p=litex.git

clean up (thanks to Sebastien)
---

diff --git a/lib/sata/k7sataphy/clocking.py b/lib/sata/k7sataphy/clocking.py
index d5a93d97..d257c7dc 100644
--- a/lib/sata/k7sataphy/clocking.py
+++ b/lib/sata/k7sataphy/clocking.py
@@ -17,9 +17,9 @@ class K7SATAPHYReconfig(Module):
 		drp = DRPBus()
 		self.comb += \
 			If(drp_sel,
-				Record.connect(drp, mmcm_drp),
+				drp.connect(mmcm_drp)
 			).Else(
-				Record.connect(drp, channel_drp)
+				drp.connect(channel_drp)
 			)
 
 class K7SATAPHYClocking(Module):
diff --git a/lib/sata/k7sataphy/ctrl.py b/lib/sata/k7sataphy/ctrl.py
index 873defbe..7f63b0f3 100644
--- a/lib/sata/k7sataphy/ctrl.py
+++ b/lib/sata/k7sataphy/ctrl.py
@@ -9,15 +9,13 @@ from lib.sata.k7sataphy.std import *
 # Todo:
 # rx does not use the same clock, need to resynchronize signals.
 
-def us(t, speed="SATA3", margin=True):
+def us(t, speed="SATA3"):
 	clk_freq = {
 		"SATA3" :	300*1000000,
 		"SATA2" :	150*1000000,
 		"SATA1" :	 75*1000000
 	}
 	clk_period_us = 1000000/clk_freq[speed]
-	if margin:
-		t += clk_period_us/2
 	return ceil(t/clk_period_us)
 
 class K7SATAPHYHostCtrl(Module):