From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 6 Apr 2021 20:38:04 +0000 (+0100)
Subject: 8-bit granularity on JTAG wishbone
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c016bf7a099994cb3bd5ce66efd9b622521bd8e3;p=soc.git

8-bit granularity on JTAG wishbone
---

diff --git a/src/soc/debug/jtag.py b/src/soc/debug/jtag.py
index 5cac2cd4..c2a6f095 100644
--- a/src/soc/debug/jtag.py
+++ b/src/soc/debug/jtag.py
@@ -82,6 +82,7 @@ class JTAG(DMITAP, Pins):
         # create and connect wishbone
         self.wb = self.add_wishbone(ircodes=[5, 6, 7], features={'err'},
                                    address_width=29, data_width=wb_data_wid,
+                                   granularity=8, # 8-bit wide
                                    name="jtag_wb")
 
         # create DMI2JTAG (goes through to dmi_sim())