From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 18 Nov 2017 08:56:36 +0000 (+0100)
Subject: Merge pull request #453 from dh73/master
X-Git-Tag: yosys-0.8~273
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c01df04e32f7913622f40ced56fcb523ac96d35f;p=yosys.git

Merge pull request #453 from dh73/master

Updating Intel FPGA subsystem with Cyclone 10, minor changes in examples/intel directory and Speedster cells
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c01df04e32f7913622f40ced56fcb523ac96d35f