From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Mon, 4 Apr 2016 23:56:43 +0000 (-0700)
Subject: Added GP_BANDGAP cell
X-Git-Tag: yosys-0.7~263^2~5
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c01ff05fabe948acfbbb259e92b3bd0009bd068e;p=yosys.git

Added GP_BANDGAP cell
---

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 4ea576960..d98526215 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -144,3 +144,12 @@ module GP_SYSRESET(input RST);
 	//cannot simulate whole system reset
 	
 endmodule
+
+module GP_BANDGAP(output reg OK, output reg VOUT);
+	parameter AUTO_PWRDN = 1;
+	parameter CHOPPER_EN = 1;
+	parameter OUT_DELAY = 100;
+	
+	//cannot simulate mixed signal IP
+	
+endmodule