From: Luke Kenneth Casson Leighton Date: Wed, 26 May 2021 15:10:30 +0000 (+0100) Subject: arse. PLL test_issuer clk_sel_i accidentally only 1 bit not 2 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c0240215a3d7f2e76302f895dc9b1411d2dfd683;p=soc.git arse. PLL test_issuer clk_sel_i accidentally only 1 bit not 2 --- diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index 55ca0902..d8a3d486 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -1235,7 +1235,7 @@ class TestIssuer(Elaboratable): if self.pll_en: self.pll_test_o = Signal(reset_less=True) self.pll_vco_o = Signal(reset_less=True) - self.clk_sel_i = Signal(reset_less=True) + self.clk_sel_i = Signal(2, reset_less=True) def elaborate(self, platform): m = Module()