From: lkcl <lkcl@web>
Date: Sun, 15 Oct 2023 20:52:19 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c02424b1630600bc191dbbf6cff02666a0ec75dc;p=libreriscv.git

---

diff --git a/openpower/isa.mdwn b/openpower/isa.mdwn
index df1797b0b..b3412ec4d 100644
--- a/openpower/isa.mdwn
+++ b/openpower/isa.mdwn
@@ -40,6 +40,7 @@ Explanation of the rules for twin register targets
 * [[isa/svfixedarith]]
 * [[isa/svfparith]]
 * [[isa/bitmanip]]
+* [[isa/av]] - Audio/Video includes minmax, sum of absolute difference etc.
 
 Scalar "Post-Increment" Draft Load/Store with Update