From: lkcl <lkcl@web>
Date: Tue, 7 Sep 2021 16:01:47 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~195
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c02770d0d56b3db403a40474e6ba25c95e63d1fb;p=libreriscv.git

---

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 43f44f0bb..ba0e47cf5 100644
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -1,8 +1,9 @@
 # Condition Register SVP64 Operations
 
 Condition Register Fields are only 4 bits wide: this presents some
-interesting conceptual challenges for SVP64, oarticularly with respect to element
+interesting conceptual challenges for SVP64, particularly with respect to element
 width (which is clearly meaningless). Likewise, arithmetic saturation
+(an important part of Arithmetic SVP64)
 has no meaning. Consequently an alternative Mode Format is required.
 
 This alternative mapping **only** applies to instructions that **only**