From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 27 Dec 2021 18:52:05 +0000 (+0000)
Subject: found bug in mmu with calculating addrsh, should have been a right
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c030176faf54e1941c75fc6a4bfb6ecc6a280440;p=soc.git

found bug in mmu with calculating addrsh, should have been a right
shift
---

diff --git a/src/soc/experiment/mmu.py b/src/soc/experiment/mmu.py
index 5787f110..a245ddbd 100644
--- a/src/soc/experiment/mmu.py
+++ b/src/soc/experiment/mmu.py
@@ -522,7 +522,7 @@ class MMU(Elaboratable):
 
         # Shift address bits 61--12 right by 0--47 bits and
         # supply the least significant 16 bits of the result.
-        comb += addrsh.eq(r.addr[12:62] << r.shift)
+        comb += addrsh.eq(r.addr[12:62] >> r.shift)
 
         with m.If(r.state != State.IDLE):
             sync += Display("MMU state %d %016x", r.state, data)