From: lkcl Date: Wed, 23 Jun 2021 10:49:12 +0000 (+0100) Subject: (no commit message) X-Git-Tag: DRAFT_SVP64_0_1~725 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c03fff21d00c388a6f0fc08c1f962a71dace2f0e;p=libreriscv.git --- diff --git a/openpower/isa/svfixedload.mdwn b/openpower/isa/svfixedload.mdwn new file mode 100644 index 000000000..72e33d9c6 --- /dev/null +++ b/openpower/isa/svfixedload.mdwn @@ -0,0 +1,178 @@ + + +# Load Byte and Zero + +SVD-Form + +* lbz RT,D(RA) + +Pseudo-code: + + b <- (RA|0) + EA <- b + EXTS(D) + RT <- [0]*56 || MEM(EA, 1) + +Special Registers Altered: + + None + +# Load Byte and Zero with Update + +D-Form + +* lbzu RT,D(RA) + +Pseudo-code: + + EA <- (RA) + EXTS(D) + RT <- [0] * 56 || MEM(EA, 1) + RA <- EA + +Special Registers Altered: + + None + +# Load Halfword and Zero + +D-Form + +* lhz RT,D(RA) + +Pseudo-code: + + b <- (RA|0) + EA <- b + EXTS(D) + RT <- [0] * 48 || MEM(EA, 2) + +Special Registers Altered: + + None + +# Load Halfword and Zero with Update + +D-Form + +* lhzu RT,D(RA) + +Pseudo-code: + + EA <- (RA) + EXTS(D) + RT <- [0] * 48 || MEM(EA, 2) + RA <- EA + +Special Registers Altered: + + None + +# Load Halfword Algebraic + +D-Form + +* lha RT,D(RA) + +Pseudo-code: + + b <- (RA|0) + EA <- b + EXTS(D) + RT <- EXTS(MEM(EA, 2)) + +Special Registers Altered: + + None + +# Load Halfword Algebraic with Update + +D-Form + +* lhau RT,D(RA) + +Pseudo-code: + + EA <- (RA) + EXTS(D) + RT <- EXTS(MEM(EA, 2)) + RA <- EA + +Special Registers Altered: + + None + +# Load Word and Zero + +D-Form + +* lwz RT,D(RA) + +Pseudo-code: + + b <- (RA|0) + EA <- b + EXTS(D) + RT <- [0] * 32 || MEM(EA, 4) + +Special Registers Altered: + + None + +# Load Word and Zero with Update + +D-Form + +* lwzu RT,D(RA) + +Pseudo-code: + + EA <- (RA) + EXTS(D) + RT <- [0]*32 || MEM(EA, 4) + RA <- EA + +Special Registers Altered: + + None + +# Load Word Algebraic + +DS-Form + +* lwa RT,DS(RA) + +Pseudo-code: + + b <- (RA|0) + EA <- b + EXTS(DS || 0b00) + RT <- EXTS(MEM(EA, 4)) + +Special Registers Altered: + + None + +# Load Doubleword + +DS-Form + +* ld RT,DS(RA) + +Pseudo-code: + + b <- (RA|0) + EA <- b + EXTS(DS || 0b00) + RT <- MEM(EA, 8) + +Special Registers Altered: + + None + +# Load Doubleword with Update Indexed + +DS-Form + +* ldu RT,DS(RA) + +Pseudo-code: + + EA <- (RA) + EXTS(DS || 0b00) + RT <- MEM(EA, 8) + RA <- EA + +Special Registers Altered: + + None +