From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 12 Jun 2019 23:54:12 +0000 (-0700)
Subject: Update CHANGELOG
X-Git-Tag: working-ls180~1237^2~133
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c04482b07798cfcca3218cfafe0998eeb6a88f76;p=yosys.git

Update CHANGELOG
---

diff --git a/CHANGELOG b/CHANGELOG
index 839fefcf1..6e3faa9ff 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -17,6 +17,7 @@ Yosys 0.8 .. Yosys 0.8-dev
     - Added "rename -src"
     - Added "equiv_opt" pass
     - Added "read_aiger" frontend
+    - Added "abc9" pass (experimental, accessible using synth_xilinx -abc9 and synth_ice40 -abc9)
     - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"