From: whitequark <whitequark@whitequark.org>
Date: Thu, 20 Dec 2018 07:59:40 +0000 (+0000)
Subject: manual: fix typos.
X-Git-Tag: yosys-0.9~360^2^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c04908c99740e616cae454aa6a5d7a3dd13af2fa;p=yosys.git

manual: fix typos.
---

diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index 6589bb2e7..65a79020f 100644
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -254,7 +254,7 @@ enable bit for each data bit), an address input \B{ADDR} and a data input
 
 \begin{itemize}
 \item \B{MEMID} \\
-The name of the RTLIL::Memory object that is associated with this read port.
+The name of the RTLIL::Memory object that is associated with this write port.
 
 \item \B{ABITS} \\
 The number of address bits (width of the \B{ADDR} input port).
@@ -263,7 +263,7 @@ The number of address bits (width of the \B{ADDR} input port).
 The number of data bits (width of the \B{DATA} output port).
 
 \item \B{CLK\_ENABLE} \\
-When this parameter is non-zero, the clock is used. Otherwise this read port is asynchronous and
+When this parameter is non-zero, the clock is used. Otherwise this write port is asynchronous and
 the \B{CLK} input is not used.
 
 \item \B{CLK\_POLARITY} \\