From: Xan Date: Wed, 25 Apr 2018 11:51:28 +0000 (+0100) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~5516 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c049bdfd569c9f35cfb38524f1376a97e8dc0548;p=libreriscv.git --- diff --git a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn index 74df58b41..ca8055d81 100644 --- a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn +++ b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn @@ -1,6 +1,6 @@ # Comparative analysis of Andes Packed ISA proposal vs Harmonised RVP -Harmonised RVP is a proposal to provide SIMD functionality comparable to the Andes Packed SIMD, but in a manner that is forwards compatible ("harmonised") with the RV Vector specification. +Harmonised RVP is a proposal to provide SIMD functionality comparable to the Andes Packed SIMD ISA, but in a manner that is forwards compatible ("harmonised") with the RV Vector specification. An example use case is a string copy operation - using Harmonised RVP, binary code using integer register based SIMD to copy a string of bytes can also execute (unchanged) on a full RV Vector processor and use the dedicated vector unit to copy string. The is also upwards compatibility between RV32 and RV64 SIMD using this same approach.