From: Jakub Jelinek Date: Thu, 12 May 2016 08:34:11 +0000 (+0200) Subject: sse.md (pinsr_evex_isa): New mode attr. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c05d08f6fadfa78b0aad8f8ffa5a8504b44a9467;p=gcc.git sse.md (pinsr_evex_isa): New mode attr. * config/i386/sse.md (pinsr_evex_isa): New mode attr. (_pinsr): Add 2 alternatives with v constraints instead of x and isa attribute. * gcc.target/i386/avx512bw-vpinsr-1.c: New test. * gcc.target/i386/avx512dq-vpinsr-1.c: New test. * gcc.target/i386/avx512vl-vpinsr-1.c: New test. From-SVN: r236165 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 153c0a7d085..4dbae25dfe9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,9 @@ 2016-05-12 Jakub Jelinek + * config/i386/sse.md (pinsr_evex_isa): New mode attr. + (_pinsr): Add 2 alternatives with + v constraints instead of x and isa attribute. + PR target/71019 * config/i386/sse.md (_packssdw, _packusdw): Make sure EVEX encoded insn diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 6c5dd62e7b4..82562baa98d 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -12036,13 +12036,17 @@ [(V16QI "sse4_1") (V8HI "sse2") (V4SI "sse4_1") (V2DI "sse4_1")]) +(define_mode_attr pinsr_evex_isa + [(V16QI "avx512bw") (V8HI "avx512bw") + (V4SI "avx512dq") (V2DI "avx512dq")]) + ;; sse4_1_pinsrd must come before sse2_loadld since it is preferred. (define_insn "_pinsr" - [(set (match_operand:PINSR_MODE 0 "register_operand" "=x,x,x,x") + [(set (match_operand:PINSR_MODE 0 "register_operand" "=x,x,x,x,v,v") (vec_merge:PINSR_MODE (vec_duplicate:PINSR_MODE - (match_operand: 2 "nonimmediate_operand" "r,m,r,m")) - (match_operand:PINSR_MODE 1 "register_operand" "0,0,x,x") + (match_operand: 2 "nonimmediate_operand" "r,m,r,m,r,m")) + (match_operand:PINSR_MODE 1 "register_operand" "0,0,x,x,v,v") (match_operand:SI 3 "const_int_operand")))] "TARGET_SSE2 && ((unsigned) exact_log2 (INTVAL (operands[3])) @@ -12059,16 +12063,18 @@ case 1: return "pinsr\t{%3, %2, %0|%0, %2, %3}"; case 2: + case 4: if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (SImode)) return "vpinsr\t{%3, %k2, %1, %0|%0, %1, %k2, %3}"; /* FALLTHRU */ case 3: + case 5: return "vpinsr\t{%3, %2, %1, %0|%0, %1, %2, %3}"; default: gcc_unreachable (); } } - [(set_attr "isa" "noavx,noavx,avx,avx") + [(set_attr "isa" "noavx,noavx,avx,avx,,") (set_attr "type" "sselog") (set (attr "prefix_rex") (if_then_else @@ -12089,7 +12095,7 @@ (const_string "*") (const_string "1"))) (set_attr "length_immediate" "1") - (set_attr "prefix" "orig,orig,vex,vex") + (set_attr "prefix" "orig,orig,vex,vex,evex,evex") (set_attr "mode" "TI")]) (define_expand "_vinsert_mask" diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index ec16edd781d..d893b58a590 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,9 @@ 2016-05-12 Jakub Jelinek + * gcc.target/i386/avx512bw-vpinsr-1.c: New test. + * gcc.target/i386/avx512dq-vpinsr-1.c: New test. + * gcc.target/i386/avx512vl-vpinsr-1.c: New test. + PR target/71019 * gcc.target/i386/avx512vl-pack-1.c: New test. * gcc.target/i386/avx512vl-pack-2.c: New test. diff --git a/gcc/testsuite/gcc.target/i386/avx512bw-vpinsr-1.c b/gcc/testsuite/gcc.target/i386/avx512bw-vpinsr-1.c new file mode 100644 index 00000000000..ff66dd4fd33 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512bw-vpinsr-1.c @@ -0,0 +1,33 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mavx512vl -mavx512bw" } */ + +typedef char v16qi __attribute__((vector_size (16))); +typedef short v8hi __attribute__((vector_size (16))); + +v16qi +f1 (v16qi a, char b) +{ + register v16qi c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + v16qi d = c; + ((char *) &d)[3] = b; + c = d; + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler "vpinsrb\[^\n\r]*xmm16" } } */ + +v8hi +f2 (v8hi a, short b) +{ + register v8hi c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + v8hi d = c; + ((short *) &d)[3] = b; + c = d; + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler "vpinsrw\[^\n\r]*xmm16" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512dq-vpinsr-1.c b/gcc/testsuite/gcc.target/i386/avx512dq-vpinsr-1.c new file mode 100644 index 00000000000..427b4e73a16 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512dq-vpinsr-1.c @@ -0,0 +1,33 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mavx512vl -mavx512dq" } */ + +typedef int v4si __attribute__((vector_size (16))); +typedef long long v2di __attribute__((vector_size (16))); + +v4si +f1 (v4si a, int b) +{ + register v4si c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + v4si d = c; + ((int *) &d)[3] = b; + c = d; + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler "vpinsrd\[^\n\r]*xmm16" } } */ + +v2di +f2 (v2di a, long long b) +{ + register v2di c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + v2di d = c; + ((long long *) &d)[1] = b; + c = d; + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler "vpinsrq\[^\n\r]*xmm16" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpinsr-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpinsr-1.c new file mode 100644 index 00000000000..9cfab9bf542 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpinsr-1.c @@ -0,0 +1,63 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mavx512vl -mno-avx512bw -mno-avx512dq" } */ + +typedef char v16qi __attribute__((vector_size (16))); +typedef short v8hi __attribute__((vector_size (16))); +typedef int v4si __attribute__((vector_size (16))); +typedef long long v2di __attribute__((vector_size (16))); + +v16qi +f1 (v16qi a, char b) +{ + register v16qi c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + v16qi d = c; + ((char *) &d)[3] = b; + c = d; + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler-not "vpinsrb\[^\n\r]*xmm16" } } */ + +v8hi +f2 (v8hi a, short b) +{ + register v8hi c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + v8hi d = c; + ((short *) &d)[3] = b; + c = d; + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler-not "vpinsrw\[^\n\r]*xmm16" } } */ + +v4si +f3 (v4si a, int b) +{ + register v4si c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + v4si d = c; + ((int *) &d)[3] = b; + c = d; + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler-not "vpinsrd\[^\n\r]*xmm16" } } */ + +v2di +f4 (v2di a, char b) +{ + register v2di c __asm ("xmm16") = a; + asm volatile ("" : "+v" (c)); + v2di d = c; + ((long long *) &d)[1] = b; + c = d; + asm volatile ("" : "+v" (c)); + return c; +} + +/* { dg-final { scan-assembler-not "vpinsrq\[^\n\r]*xmm16" } } */